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| Freescale Semiconductor Technical Data Document Number: MPC8377EEC Rev. 2, 10/2009 MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications This document provides an overview of the MPC8377E PowerQUICCTM II Pro processor features, including a block diagram showing the major functional components. The device is a cost-effective, low-power, highly integrated host processor that addresses the requirements of several printing and imaging, consumer, and industrial applications, including main CPUs and I/O processors in printing systems, networking switches and line cards, wireless LANs (WLANs), network access servers (NAS), VPN routers, intelligent NIC, and industrial controllers. The MPC8377E extends the PowerQUICCTM family, adding higher CPU performance, additional functionality, and faster interfaces while addressing the requirements related to time-to-market, price, power consumption, and package size. Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 7 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 11 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 13 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 14 DDR1 and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . 16 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Ethernet: Enhanced Three-Speed Ethernet (eTSEC) 22 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Enhanced Secure Digital Host Controller (eSDHC) . 42 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Serial ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 76 Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 86 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 System Design Information . . . . . . . . . . . . . . . . . . 117 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 119 Document Revision History . . . . . . . . . . . . . . . . . . 122 1 Overview The MPC8377E incorporates the e300c4s core, which includes 32 Kbytes of L1 instruction and data caches and on-chip memory management units (MMUs). The device offers two enhanced three-speed 10, 100, 1000 Mbps Ethernet interfaces, a DDR1/DDR2 SDRAM memory controller, a flexible, a 32-bit local bus controller, a 32-bit PCI controller, an optional dedicated security engine, a USB 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. (c) Freescale Semiconductor, Inc., 2009. All rights reserved. Overview 2.0 dual-role controller, a programmable interrupt controller, dual I2C controllers, a 4-channel DMA controller, an enhanced secured digital host controller, and a general-purpose I/O port. The block diagram of the MPC8377E is shown in Figure 1. MPC8377E DUART Dual I2C Timers GPIO SPI Interrupt Controller e300 Core 32-Kbyte D-Cache 32-Kbyte I-Cache DDR1/DDR2 SDRAM Controller Security Enhanced Local Bus USB 2.0 Hi-Speed DMA PCI Host Device eTSEC RGMII, RMII, RTBI, MII eTSEC RGMII, RMII, RTBI, MII SATA PHY PHY PCI Express x1 PCI Express x1 Figure 1. MPC8377E Block Diagram and Features The following features are supported in the MPC8377E: * e300c4s core built on Power ArchitectureTM technology with 32-Kbyte instruction cache and 32-Kbyte data cache, a floating point unit, and two integer units * DDR1/DDR2 memory controller supporting a 32/64-bit interface * Peripheral interfaces, such as a 32-bit PCI interface with up to 66-MHz operation * 32-bit local bus interface running up to 133-MHz * USB 2.0 (full/high speed) support * Power management controller for low-power consumption * High degree of software compatibility with previous-generation PowerQUICC processor-based designs for backward compatibility and easier software migration * Optional security engine provides acceleration for control and data plane security protocols The optional security engine (SEC 3.0) is noted with the extension "E" at the end. It allows CPU-intensive cryptographic operations to be offloaded from the main CPU core. The security-processing accelerator provides hardware acceleration for the DES, 3DES, AES, SHA-1, and MD-5 algorithms. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 2 Freescale Semiconductor Overview In addition to the security engine, new high-speed interfaces such as PCI Express and SATA are included. Table 1 compares the differences between MPC837xE derivatives and provides the number of ports available for each interface. Table 1. High-Speed Interfaces on the MPC8377E, MPC8378E, and MPC8379E Descriptions SGMII PCI Express(R) SATA MPC8377E 0 2 2 MPC8378E 2 2 0 MPC8379E 0 0 4 1.1 DDR Memory Controller The DDR1/DDR2 memory controller includes the following features: * Single 32- or 64-bit interface supporting both DDR1 and DDR2 SDRAM * Support for up to 400-MHz data rate * Support up to 4 chip selects * 64-Mbit to 2-Gbit (for DDR1) and to 4-Gbit (for DDR2) devices with x8/x16/x32 data ports (no direct x4 support) * Support for up to 32 simultaneous open pages * Supports auto refresh * On-the-fly power management using CKE * 1.8-/2.5-V SSTL2 compatible I/O 1.2 USB Dual-Role Controller The USB controller includes the following features: * Supports USB on-the-go mode, including both device and host functionality, when using an external ULPI (UTMI + low-pin interface) PHY * Complies with USB Specification, Rev. 2.0 * Supports operation as a stand-alone USB device -- Supports one upstream facing port -- Supports three programmable USB endpoints * Supports operation as a stand-alone USB host controller -- Supports USB root hub with one downstream-facing port -- Enhanced host controller interface (EHCI) compatible * Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operation; low-speed operation is supported only in host mode * Supports UTMI + low pin interface (ULPI) MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 3 Overview 1.3 Dual Enhanced Three-Speed Ethernet Controllers (eTSECs) The eTSECs include the following features: * Two enhanced Ethernet interfaces can be used for RGMII/MII/RMII/RTBI * Two controllers conform to IEEE Std 802.3(R), IEEE 802.3u, IEEE 802.3x, IEEE 802.3z, IEEE 802.3au, IEEE 802.3ab, and IEEE Std 1588TM standards * Support for Wake-on-Magic PacketTM, a method to bring the device from standby to full operating mode * MII management interface for external PHY control and status 1.4 Integrated Programmable Interrupt Controller (IPIC) The integrated programmable interrupt controller (IPIC) implements the necessary functions to provide a flexible solution for general-purpose interrupt control. The IPIC programming model is compatible with the MPC8260 interrupt controller, and it supports 8 external and 34 internal discrete interrupt sources. Interrupts can also be redirected to an external interrupt controller. 1.5 Power Management Controller (PMC) The power management controller includes the following features: * Provides power management when the device is used in both host and agent modes * Supports PCI Power Management 1.2 D0, D1, D2, and D3hot states * Support for PME generation in PCI agent mode, PME detection in PCI host mode * Supports Wake-on-LAN (Magic Packet), USB, GPIO, and PCI (PME input as host) * Supports MPC8349E backward-compatibility mode 1.6 Serial Peripheral Interface (SPI) The serial peripheral interface (SPI) allows the device to exchange data between other PowerQUICC family chips, Ethernet PHYs for configuration, and peripheral devices such as EEPROMs, real-time clocks, A/D converters, and ISDN devices. The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface (receive, transmit, clock, and slave select). The SPI block consists of transmitter and receiver sections, an independent baud-rate generator, and a control unit. 1.7 DMA Controller, Dual I2C, DUART, Enhanced Local Bus Controller (eLBC), and Timers The device provides an integrated four-channel DMA controller with the following features: * Allows chaining (both extended and direct) through local memory-mapped chain descriptors (accessible by local masters) * Supports misaligned transfers MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 4 Freescale Semiconductor Overview There are two I2C controllers. These synchronous, multi-master buses can be connected to additional devices for expansion and system development. The DUART supports full-duplex operation and is compatible with the PC16450 and PC16550 programming models. 16-byte FIFOs are supported for both the transmitter and the receiver. The main component of the enhanced local bus controller (eLBC) is its memory controller, which provides a seamless interface to many types of memory devices and peripherals. The memory controller is responsible for controlling eight memory banks shared by a NAND Flash control machine (FCM), a general-purpose chip-select machine (GPCM), and up to three user-programmable machines (UPMs). As such, it supports a minimal glue logic interface to SRAM, EPROM, NOR Flash EPROM, NAND Flash, EPROM, burstable RAM, regular DRAM devices, extended data output DRAM devices, and other peripherals. The eLBC external address latch enable (LALE) signal allows multiplexing of addresses with data signals to reduce the device pin count. The enhanced local bus controller also includes a number of data checking and protection features, such as data parity generation and checking, write protection, and a bus monitor to ensure that each bus cycle is terminated within a user-specified period. The local bus can operate at up to 133 MHz. The system timers include the following features: periodic interrupt timer, real time clock, software watchdog timer, and two general-purpose timer blocks. 1.8 Security Engine The optional security engine is optimized to handle all the algorithms associated with IPSec, IEEE 802.11i, and iSCSI. The security engine contains one crypto-channel, a controller, and a set of crypto execution units (EUs). The execution units are: * Data encryption standard execution unit (DEU), supporting DES and 3DES * Advanced encryption standard unit (AESU), supporting AES * Message digest execution unit (MDEU), supporting MD5, SHA1, SHA-256, and HMAC with any algorithm * One crypto-channel supporting multi-command descriptor chains 1.9 PCI Controller The PCI controller includes the following features: * PCI Specification Revision 2.3 compatible * Single 32-bit data PCI interface operates at up to 66 MHz * PCI 3.3-V compatible (not 5-V compatible) * Support for host and agent modes * On-chip arbitration, supporting 5 external masters on PCI * Selectable hardware-enforced coherency MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 5 Overview 1.10 PCI Express(R) Controller The PCI Express(R) controller includes the following features: * PCI Express 1.0a compatible * Two x1 links or one x2 link width * Auto-detection of number of connected lanes * Selectable operation as root complex or endpoint * Both 32- and 64-bit addressing * 128-byte maximum payload size * Support for MSI and INTx interrupt messages * Virtual channel 0 only * Selectable Traffic Class * Full 64-bit decode with 32-bit wide windows * Dedicated four channel descriptor-based DMA engine per interface 1.11 Serial ATA (SATA) Controllers The serial ATA (SATA) controllers have the following features: * Supports Serial ATA Rev 2.5 Specification * Spread spectrum clocking on receive * Asynchronous notification * Hot Plug including asynchronous signal recovery * Link power management * Native command queuing * Staggered spin-up and port multiplier support * Port multiplier support * SATA 1.5 and 3.0 Gb/s operation * Interrupt driven * Power management support * Error handling and diagnostic features -- Far end/near end loopback -- Failed CRC error reporting -- Increased ALIGN insertion rates * Scrambling and CONT override 1.12 Enhanced Secured Digital Host Controller (eSDHC) The enhanced SD Host Controller (eSDHC) has the following features: * Conforms to SD Host Controller Standard Specification, Rev 2.0 with Test Event register support. * Compatible with the MMC System Specification, Rev 4.0 MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 6 Freescale Semiconductor Electrical Characteristics * * * * * * Compatible with the SD Memory Card Specification, Rev 2.0, and supports High Capacity SD memory cards Compatible with the SDIO Card Specification Rev, 1.2 Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD Combo, MMC, MMCplus, MMC 4x, and RS-MMC cards SD bus clock frequency up to 50 MHz Supports 1-/4-bit SD and SDIO modes, 1-/4-bit MMC modes Supports internal DMA capabilities 2 Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8377E. The device is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. 2.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. 2.1.1 Absolute Maximum Ratings Table 2. Absolute Maximum Ratings 1 Characteristic Symbol VDD AVDD GVDD LVDD[1,2] I2C, and OVDD LBVDD L[1,2]_nVDD DDR DRAM signals DDR DRAM reference Three-speed Ethernet signals PCI, DUART, CLKIN, system control and power management, I2C, and JTAG signals Local Bus MVIN MVREF LVIN OVIN LBIN Max Value -0.3 to 1.1 -0.3 to 1.1 -0.3 to 2.75 -0.3 to 1.98 -0.3 to 3.63 -0.3 to 3.63 -0.3 to 3.63 -0.3 to 1.1 -0.3 to (GVDD + 0.3) -0.3 to (GVDD + 0.3) -0.3 to (LVDD + 0.3) -0.3 to (OVDD + 0.3) -0.3 to (LBVDD + 0.3) Unit V V V V V V V V V V V V Notes -- -- -- -- -- -- 6 2, 4 2, 4 -- 3, 4 5 Table 2 provides the absolute maximum ratings. Core supply voltage PLL supply voltage (e300 core, system and eLBC) DDR1 and DDR2 DRAM I/O voltage Three-speed Ethernet I/O, MII management voltage PCI, DUART, system control and power management, JTAG I/O voltage Local bus SerDes Input voltage MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 7 Electrical Characteristics Table 2. Absolute Maximum Ratings 1 (continued) Characteristic Storage temperature range Symbol TSTG Max Value -55 to 150 Unit C Notes -- Notes: 1 Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2 Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3 Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4 (M,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2. 5 OV on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as IN shown in Figure 2. 6 L[1,2]_nVDD includes SDAVDD_0, XCOREV DD, and XPADVDD power inputs. 2.1.2 Power Supply Voltage Specification Table 3 provides the recommended operating conditions for the device. Note that the values in Table 3 are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. Table 3. Recommended Operating Conditions Characteristic Core supply voltage up to 667 MHz 800 MHz PLL supply voltage (e300 core, system, and eLBC) DDR1 and DDR2 DRAM I/O voltage Three-speed Ethernet I/O, MII management voltage PCI, local bus, DUART, system control and power management, I2C, and JTAG I/O voltage Local Bus up to 667 MHz 800 MHz GVDD LV DD[1,2] OVDD LBV DD AVDD Symbol VDD Recommended Value 1.0 50 mV 1.05 50 mV 1.0 50 mV 1.05 50 mV 2.5 V 125 mV 1.8 V 90 mV 3.3 V 165 mV 2.5 V 125 mV 3.3 V 165 mV 1.8 V 90 mV 2.5 V 125 mV 3.3 V 165 mV 1.0 50 mV 1.05 V 50 mV Unit V V V V V V V V Notes 1 1 1 1 1 -- 1 -- SerDes up to 667 MHz 800 MHz L[1,2]_nVDD V V 1, 2 1, 2 MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 8 Freescale Semiconductor Electrical Characteristics Table 3. Recommended Operating Conditions (continued) Characteristic Operating temperature range commerical extended temperature Symbol Ta Tj Ta Tj Recommended Value Ta=0 (min)-- Tj=125 (max) Ta=-40 (min)-- Tj=125 (max) Unit C C Notes -- -- Notes: 1 GVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction--either in the positive or negative direction. 2 L[1,2]_nVDD, SDAVDD_0, XCOREVDD, and XPADVDD power inputs. Figure 2 shows the undershoot and overshoot voltages at the interfaces of the device. G/L/OVDD + 20% G/L/OVDD + 5% VIH G/L/OVDD GND GND - 0.3 V VIL GND - 0.7 V Not to Exceed 10% of tinterface1 Note: 1. Note that tinterface refers to the clock period associated with the bus clock interface. 2. Please note that with the PCI overshoot allowed (as specified above), the device does not fully comply with the maximum AC ratings and device protection guideline outlined in the PCI Rev. 2.3 Specification (Section 4.2.2.3). Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 9 Electrical Characteristics 2.1.3 Output Driver Characteristics Table 4 provides information on the characteristics of the output driver strengths. The values are preliminary estimates. Table 4. Output Drive Capability Driver Type 1 Local bus interface utilities signals Output Impedance () 45 40 PCI signals DDR1 signal DDR2 signal eTSEC 10/100/1000 signals DUART, system control, I2C, JTAG, SPI, and USB GPIO signals 1 Supply Voltage LBVDD = 2.5 V, 3.3 V LBVDD = 1.8 V OVDD = 3.3 V GVDD = 2.5 V GVDD = 1.8 V LVDD = 2.5 V, 3.3 V OVDD = 3.3 V OVDD = 3.3 V 25 18 18 45 45 45 Specialized SerDes output capabilities are described in the relevant sections of these specifications (such as PCI Express and SATA) 2.2 Power Sequencing The device requires its power rails to be applied in a specific sequence in order to ensure proper device operation. During the power ramp up, before the power supplies are stable and if the I/O voltages are supplied before the core voltage, there may be a period of time that all input and output pins will actively be driven and cause contention and excessive current. To avoid actively driving the I/O pins and to eliminate excessive current draw, apply the core voltages (VDD and AVDD) before the I/O voltages and assert PORESET before the power supplies fully ramp up. VDD and AVDD must reach 90% of their nominal value before GVDD, LVDD, and OVDD reach 10% of their value, see Figure 3. I/O voltage supplies, GVDD, LVDD, and OVDD do not have any ordering requirements with respect to one another. V I/O Voltage (GVDD, LVDD, and OVDD) Core Voltage (VDD, AVDD) 90% 0.7 V 0 t Figure 3. Power-Up Sequencing Example MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 10 Freescale Semiconductor Power Characteristics Please note that the SerDes power supply (L[1,2]_nVDD) should follow the same timing as the core supply (VDD). The opposite sequence applies to the power down requirements. The I/O supplies must go down first and immediately followed by the core and PLL supplies. 3 Power Characteristics Table 5. MPC8377E Power Dissipation 1 The estimated typical power dissipation for the MPC8377E device is shown in Table 5. Core Frequency CSB/DDR Frequency Sleep Power Typical Application Typical Application Max Application (MHz) (MHz) at Tj = 65C (W) 2 at Tj = 65C (W) 2 at Tj = 125C (W) 3 at Tj = 125C (W) 4 333 333 167 400 400 266 300 450 225 333 500 250 355 533 266 400 600 300 333 667 266 800 1 1.45 1.45 1.45 1.45 1.45 1.45 1.45 1.45 1.45 1.45 1.45 1.45 1.45 1.45 1.45 1.9 1.8 2.0 1.9 2.0 1.9 2.0 1.9 2.0 2.0 2.1 2.0 2.1 2.0 2.5 3.2 3.0 3.3 3.1 3.2 3.1 3.3 3.2 3.3 3.2 3.4 3.3 3.3 3.3 3.8 3.8 3.6 4.0 3.8 3.8 3.7 3.9 3.8 4.0 3.9 4.1 4.0 4.1 3.9 4.3 400 Note: The values do not include I/O supply power (OV DD, LVDD, GVDD) or AVDD. For I/O power values, see Table 6. 2 Typical power is based on a voltage of V DD = 1.0 V for core frequences 667 MHz or VDD = 1.05 V for core frequences of 800 MHz, and running a Dhrystone benchmark application. 3 Typical power is based on a voltage of V DD = 1.0 V for core frequences 667 MHz or VDD = 1.05 V for core frequences of 800 MHz, and running a Dhrystone benchmark application. 4 Maximum power is based on a voltage of V DD = 1.0 V for core frequences 667 MHz or VDD = 1.05 V for core frequences of 800 MHz, worst case process, and running an artificial smoke test. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 11 Power Characteristics Table 6 shows the estimated typical I/O power dissipation for the device. Table 6. MPC8377E Typical I/O Power Dissipation Interface Parameter 200 MHz data rate, 32-bit 200 MHz data rate, 64-bit 266 MHz data rate, 32-bit 266 MHz data rate, 64-bit DDR I/O 65% utilization 2 pair of clocks 300 MHz data rate, 32-bit 300 MHz data rate, 64-bit 333 MHz data rate, 32-bit 333 MHz data rate, 64-bit 400 MHz data rate, 32-bit 400 MHz data rate, 64-bit PCI I/O Load = 30 pf 33 MHz, 32-bit 66 MHz, 32-bit 167 MHz, 32-bit 133 MHz, 32-bit 83 MHz, 32-bit 66 MHz, 32-bit 50 MHz, 32-bit GVDD (1.8 V) 0.28 0.41 0.31 0.46 0.33 0.48 0.35 0.51 0.38 GVDD/LBVDD (2.5 V) 0.35 0.49 0.4 0.56 0.43 0.6 0.45 0.64 -- OVDD LVDD LVDD L[1,2]_nVDD (3.3 V) (3.3 V) (2.5 V) (1.0 V) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit W W W W W W W W W Comments -- 0.56 -- -- -- -- -- W -- -- 0.09 0.07 0.05 0.04 0.03 -- -- 0.17 0.14 0.09 0.07 0.06 0.04 0.07 0.29 0.24 0.15 0.13 0.1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- W W W W W W W -- -- Local Bus I/O Load = 25 pf MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 12 Freescale Semiconductor Clock Input Timing Table 6. MPC8377E Typical I/O Power Dissipation (continued) Interface Parameter MII or RMII GVDD (1.8 V) -- GVDD/LBVDD (2.5 V) -- OVDD LVDD LVDD L[1,2]_nVDD (3.3 V) (3.3 V) (2.5 V) (1.0 V) -- 0.02 -- -- Unit W Comments Multiply by number of interfaces used. -- -- eTSEC I/O RGMII or Load = RTBI 25 pf USB (60MHz Clock) SerDes Other I/O 12 Mbps 480 Mbps per lane -- -- -- -- -- -- -- -- -- -- -- -- 0.01 0.2 -- -- -- -- 0.05 -- -- -- -- -- -- -- 0.029 -- W W W W W -- -- 0.01 -- Note: The values given are for typical, and not worst case, switching. 4 Clock Input Timing This section provides the clock input DC and AC electrical characteristics for the MPC8377E. Note that the PCI_CLK/PCI_SYNC_IN signal or CLKIN signal is used as the PCI input clock depending on whether the device is configured as a host or agent device. CLKIN is used when the device is in host mode. 4.1 DC Electrical Characteristics Table 7. CLKIN DC Electrical Characteristics Parameter Condition -- -- 0 V VIN OV DD 0 V VIN 0.5 V or OVDD - 0.5 V VIN OVDD Symbol VIH VIL IIN IIN Min 2.7 -0.3 -- -- Max OVDD + 0.3 0.4 10 30 Unit V V A A Notes 1 1 -- -- Table 7 provides the clock input (CLKIN/PCI_CLK) DC timing specifications for the device. Input high voltage Input low voltage CLKIN Input current PCI_CLK Input current Note: 1 In PCI agent mode, this specification does not comply with PCI 2.3 Specification. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 13 RESET Initialization 4.2 AC Electrical Characteristics The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. Table 8 provides the clock input (CLKIN/PCI_CLK) AC timing specifications for the device. Table 8. CLKIN AC Timing Specifications Parameter CLKIN/PCI_CLK frequency CLKIN/PCI_CLK cycle time CLKIN/PCI_CLK rise and fall time CLKIN/PCI_CLK duty cycle CLKIN/PCI_CLK jitter Symbol fCLKIN tCLKIN tKH, tKL tKHK/tCLKIN -- Min 25 15 0.6 40 -- Typical -- -- 1.0 -- -- Max 66.666 40 2.3 60 150 Unit MHz ns ns % ps Notes 1, 6 -- 2 3 4, 5 Notes: 1 Caution: The system, core and security block must not exceed their respective maximum or minimum operating frequencies. 2 Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 V and 2.7 V. 3 Timing is guaranteed by design and characterization. 4 This represents the total input jitter-short term and long term-and is guaranteed by design. 5 The CLKIN/PCI_CLK driver's closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter. 6 Spread spectrum is allowed up to 1% down-spread on CLKIN/PCI_CLK up to 60 KHz. 5 RESET Initialization This section describes the DC and AC electrical specifications for the reset initialization timing and electrical requirements of the MPC8377E. 5.1 RESET DC Electrical Characteristics Table 9. RESET Pins DC Electrical Characteristics Characteristic Symbol VIH VIL IIN VOH VOL VOL Condition -- -- -- IOH = -8.0 mA IOL = 8.0 mA IOL = 3.2 mA Min 2.0 -0.3 -- 2.4 -- -- Max OVDD + 0.3 0.8 30 -- 0.5 0.4 Unit V V A V V V Table 9 provides the DC electrical characteristics for the RESET pins of the device. Input high voltage Input low voltage Input current Output high voltage Output low voltage Output low voltage Note: * This table applies for pins PORESET and HRESET. The PORESET is input pin, thus stated output voltages are not relevant. * HRESET and SRESET are open drain pin, thus VOH is not relevant for these pins. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 14 Freescale Semiconductor RESET Initialization 5.2 RESET AC Electrical Characteristics Table 10. RESET Initialization Timing Specifications Parameter/Condition Min 32 32 32 512 16 4 Max -- -- -- -- -- -- Unit tPCI_SYNC_IN tCLKIN tPCI_SYNC_IN tPCI_SYNC_IN tPCI_SYNC_IN tCLKIN Notes 1 2 1 1 1 2 Table 10 provides the reset initialization AC timing specifications of the device. Required assertion time of HRESET to activate reset flow Required assertion time of PORESET with stable clock applied to CLKIN when the device is in PCI host mode Required assertion time of PORESET with stable clock applied to PCI_CLK when the device is in PCI agent mode HRESET assertion (output) HRESET negation to negation (output) Input setup time for POR config signals (CFG_RESET_SOURCE[0:3], CFG_CLKIN_DIV, and CFG_LBMUX) with respect to negation of PORESET when the device is in PCI host mode Input setup time for POR config signals (CFG_RESET_SOURCE[0:3], CFG_CLKIN_DIV, and CFG_LBMUX) with respect to negation of PORESET when the device is in PCI agent mode Input hold time for POR config signals with respect to negation of HRESET Time for the device to turn off POR config signals with respect to the assertion of HRESET Time for the device to start driving functional output signals multiplexed with the POR configuration signals with respect to the negation of HRESET 1 4 -- tPCI_SYNC_IN 1 0 -- 1 -- 4 -- ns ns tPCI_SYNC_IN -- 3 1, 3 Note: tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the primary clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the MPC8379E Integrated Host Processor Reference Manual for more details. 2t CLKIN is the clock period of the input clock applied to CLKIN. It is only valid when the device is in PCI host mode. See the MPC8379E Integrated Host Processor Reference Manual for more details. 3 POR config signals consists of CFG_RESET_SOURCE[0:3], CFG_LBMUX, and CFG_CLKIN_DIV. Table 11 provides the PLL lock times. Table 11. PLL Lock Times Parameter PLL lock times Min -- Max 100 Unit s Notes -- Note: * The device guarantees the PLL lock if the clock settings are within spec range. The core clock also depends on the core PLL ratio. See Section 23, "Clocking," for more information. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 15 DDR1 and DDR2 SDRAM 6 DDR1 and DDR2 SDRAM This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the MPC8377E. Note that DDR1 SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V. 6.1 DDR1 and DDR2 SDRAM DC Electrical Characteristics Table 12 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the device when GVDD(typ) = 1.8 V. Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V Parameter I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage Input low voltage Output leakage current Output high current (VOUT = 1.40 V) Output low current (VOUT = 0.3 V) Symbol GVDD MV REF VTT VIH VIL IOZ IOH IOL Min 1.71 0.49 x GVDD MVREF - 0.04 MVREF + 0.140 -0.3 -40 -13.4 13.4 Max 1.89 0.51 x GVDD MV REF + 0.04 GVDD + 0.3 MVREF - 0.140 40 -- -- Unit V V V V V A mA mA Notes 1 2, 5 3 -- -- 4 -- -- Note: 1 GV DD is expected to be within 50 mV of the DRAM GVDD at all times. 2 MV REF is expected to be equal to 0.5 x GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise on MVREF may not exceed 2% of the DC value. 3V TT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MVREF. This rail should track variations in the DC level of MVREF. 4 Output leakage is measured with all outputs disabled, 0 V V OUT GVDD. 5 See AN3665, MPC837xE Design Checklist, for proper DDR termination. Table 13 provides the DDR2 capacitance when GVDD(typ) = 1.8 V. Table 13. DDR2 SDRAM Capacitance for GVDD(typ) = 1.8 V Parameter Input/output capacitance: DQ, DQS, DQS Delta input/output capacitance: DQ, DQS, DQS Symbol CIO CDIO Min 6 -- Max 8 0.5 Unit pF pF Notes 1 1 Note: 1 This parameter is sampled. GVDD = 1.8 V 0.090 V, f = 1 MHz, TA = 25C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 16 Freescale Semiconductor DDR1 and DDR2 SDRAM Table 14 provides the recommended operating conditions for the DDR SDRAM component(s) when GVDD(typ) = 2.5 V. Table 14. DDR SDRAM DC Electrical Characteristics for GVDD (typ) = 2.5 V Parameter I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage Input low voltage Output leakage current Output high current (VOUT = 1.9 V) Output low current (VOUT = 0.38 V) Symbol GVDD MVREF VTT VIH VIL IOZ IOH IOL Min 2.375 0.49 x GVDD MVREF - 0.04 MVREF + 0.18 -0.3 -40 -15.2 15.2 Max 2.625 0.51 x GVDD MVREF + 0.04 GVDD + 0.3 MVREF - 0.18 40 -- -- Unit V V V V V A mA mA Notes 1 2, 5 3 -- -- 4 -- -- Note: 1 GV DD is expected to be within 50 mV of the DRAM GVDD at all times. 2 MV REF is expected to be equal to 0.5 x GVDD, and to track GV DD DC variations as measured at the receiver. Peak-to-peak noise on MVREF may not exceed 2% of the DC value. 3V TT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MVREF. This rail should track variations in the DC level of MVREF. 4 Output leakage is measured with all outputs disabled, 0 V V OUT GVDD. 5 See AN3665, MPC837xE Design Checklist, for proper DDR termination. Table 15 provides the DDR capacitance when GVDD(typ) = 2.5 V. Table 15. DDR SDRAM Capacitance for GVDD (typ) = 2.5 V Parameter Input/output capacitance: DQ, DQS Delta input/output capacitance: DQ, DQS 1 Symbol CIO CDIO Min 6 -- Max 8 0.5 Unit pF pF Notes 1 1 Note: This parameter is sampled. GVDD = 2.5 V 0.125 V, f = 1 MHz, TA = 25C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V. Table 16 provides the current draw characteristics for MVREF. Table 16. Current Draw Characteristics for MVREF Parameter Current draw for MVREF DDR1 DDR2 1 Symbol IMVREF Min Typ Max Unit A Note 1, 2 -- -- 250 150 600 400 Note: The voltage regulator for MVREF must be able to supply up to the stated maximum current. 2 This current is divided equally between MVREF1 and MVREF2, where half the current flows through each pin. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 17 DDR1 and DDR2 SDRAM 6.2 DDR1 and DDR2 SDRAM AC Electrical Characteristics This section provides the AC electrical characteristics for the DDR SDRAM interface. 6.2.1 DDR1 and DDR2 SDRAM Input AC Timing Specifications Table 17. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface Parameter Symbol VIL VIH Min -- MVREF + 0.25 Max MVREF - 0.25 -- Unit V V Table 17 provides the input AC timing specifications for the DDR2 SDRAM when GVDD(typ) = 1.8 V. AC input low voltage AC input high voltage Table 18 provides the input AC timing specifications for the DDR1 SDRAM when GVDD(typ) = 2.5 V. Table 18. DDR1 SDRAM Input AC Timing Specifications for 2.5-V Interface Parameter AC input low voltage AC input high voltage Symbol VIL VIH Min -- MVREF + 0.31 Max MVREF - 0.31 -- Unit V V Table 19 provides the input AC timing specifications for the DDR1 and DDR2 SDRAM interface. Table 19. DDR1 and DDR2 SDRAM Input AC Timing Specifications Parameter Controller skew for MDQS-MDQ/MECC/MDM 400 MHz data rate 333 MHz data rate 266 MHz data rate Symbol tCISKEW -500 -750 -750 500 750 750 Min Max Unit ps Notes 1, 2 3 -- -- Note: 1t CISKEW represents the total amount of skew consumed by the controller between MDQSn and any corresponding bit that will be captured with MDQSn. This should be subtracted from the total timing budget. 2 The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t DISKEW. This can be determined by the following equation: tDISKEW = [T/4 - |tCISKEW|] where T is the MCK clock period and |tCISKEW| is the absolute value of tCISKEW. 3 This specification applies only to DDR2 interface. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 18 Freescale Semiconductor DDR1 and DDR2 SDRAM 6.2.2 DDR1 and DDR2 SDRAM Output AC Timing Specifications Table 20. DDR1 and DDR2 SDRAM Output AC Timing Specifications Parameter Symbol1 tMCK tDDKHAS 1.95 2.40 3.15 4.20 tDDKHAX 1.95 2.40 3.15 4.20 tDDKHCS 1.95 2.40 3.15 4.20 tDDKHCX 1.95 2.40 3.15 4.20 tDDKHMH tDDKHDS, tDDKLDS -0.6 550 800 1100 1200 700 800 1100 1200 -0.5 x tMCK -0.6 -- -- -- -- 0.6 -- -- -- -- ps -- -- -- -- -0.5 x tMCK + 0.6 ns 6, 8 5, 8 ns ps 4, 8 5, 8 -- -- -- -- ns 3 -- -- -- -- ns 3 -- -- -- -- ns 3, 7 Min 5 Max 10 Unit ns ns Notes 2 3, 7 Table 20 shows the DDR1 and DDR2 SDRAM output AC timing specifications. MCKn cycle time, MCKn/MCKn crossing ADDR/CMD output setup with respect to MCK 400 MHz data rate 333 MHz data rate 266 MHz data rate 200 MHz data rate ADDR/CMD output hold with respect to MCK 400 MHz data rate 333 MHz data rate 266 MHz data rate 200 MHz data rate MCSn output setup with respect to MCK 400 MHz data rate 333 MHz data rate 266 MHz data rate 200 MHz data rate MCSn output hold with respect to MCK 400 MHz data rate 333 MHz data rate 266 MHz data rate 200 MHz data rate MCK to MDQS skew MDQ//MDM output setup with respect to MDQS 400 MHz data rate 333 MHz data rate 266 MHz data rate 200 MHz data rate MDQ//MDM output hold with respect to MDQS 400 MHz data rate 333 MHz data rate 266 MHz data rate 200 MHz data rate MDQS preamble start tDDKHDX, tDDKLDX tDDKHMP MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 19 DDR1 and DDR2 SDRAM Table 20. DDR1 and DDR2 SDRAM Output AC Timing Specifications (continued) Parameter MDQS epilogue end 1 Symbol1 tDDKHME Min -0.6 Max 0.6 Unit ns Notes 6, 8 Note: The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time. 2 All MCK/MCK referenced measurements are made from the crossing of the two signals 0.1 V. 3 ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ//MDM/MDQS. 4 Note that tDDKHMH follows the symbol conventions described in Note 1. For example, tDDKHMH describes the DDR timing (DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. See the MPC8379E PowerQUICC II Pro Host Processor Reference Manual for a description and understanding of the timing modifications enabled by use of these bits. 5 Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data MDQ, ECC, or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor. 6 All outputs are referenced to the rising edge of MCKn at the pins of the microprocessor. Note that t DDKHMP follows the symbol conventions described in Note 1. 7 Clock Control register is set to adjust the memory clocks by 1/2 the applied cycle. 8 See AN3665, "MPC837xE Design Checklist," for proper DDR termination. The minimum frequency for DDR2 is 250 MHz data rate (125 MHz clock), 167 MHz data rate (83 MHz clock) for DDR1. Figure 4 shows the DDR1 and DDR2 SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH). MCK[n] MCK[n] tMCK tDDKHMHmax) = 0.6 ns MDQS tDDKHMH(min) = -0.6 ns MDQS Figure 4. DDR Timing Diagram for tDDKHMH MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 20 Freescale Semiconductor DUART Figure 5 shows the DDR1 and DDR2 SDRAM output timing diagram. MCK[n] MCK[n] tMCK tDDKHAS ,tDDKHCS tDDKHAX ,tDDKHCX ADDR/CMD Write A0 tDDKHMP tDDKHMH MDQS[n] tDDKHDS tDDKLDS MDQ[x] tDDKHDX D0 D1 tDDKLDX tDDKHME NOOP Figure 5. DDR1 and DDR2 SDRAM Output Timing Diagram Figure 6 provides the AC test load for the DDR bus. Output Z0 = 50 GVDD/2 RL = 50 Figure 6. DDR AC Test Load 7 DUART This section describes the DC and AC electrical specifications for the DUART interface of the MPC8377E. 7.1 DUART DC Electrical Characteristics Table 21. DUART DC Electrical Characteristics Parameter Symbol VIH VIL Min 2 -0.3 Max OVDD + 0.3 0.8 Unit V V Table 21 provides the DC electrical characteristics for the DUART interface of the device. High-level input voltage Low-level input voltage OVDD MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 21 Ethernet: Enhanced Three-Speed Ethernet (eTSEC) Table 21. DUART DC Electrical Characteristics (continued) High-level output voltage, IOH = -100 A Low-level output voltage, IOL = 100 A Input current, (0 V VIN OVDD) VOH VOL IIN OVDD - 0.2 -- -- -- 0.2 30 V V A Note: * The symbol VIN, in this case, represents the OVIN symbol referenced in Table 2. 7.2 DUART AC Electrical Specifications Table 22. DUART AC Timing Specifications Parameter Value 256 > 1,000,000 16 Unit baud baud -- Notes -- 1 2 Table 22 provides the AC timing parameters for the DUART interface of the device. Minimum baud rate Maximum baud rate Oversample rate Notes: 1 Actual attainable baud rate will be limited by the latency of interrupt processing. 2 The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each 16th sample. 8 Ethernet: Enhanced Three-Speed Ethernet (eTSEC) This section provides the AC and DC electrical characteristics for the enhanced three-speed Ethernet controller. 8.1 Enhanced Three-Speed Ethernet Controller (eTSEC) (10/100/1000 Mbps)--MII/RGMII/RTBI/RMII DC Electrical Characteristics The electrical characteristics specified here apply to media independent interface (MII), reduced gigabit media independent interface (RGMII), reduced ten-bit interface (RTBI), reduced media independent interface (RMII) signals, management data input/output (MDIO) and management data clock (MDC). The MII and RMII interfaces are defined for 3.3 V, while the RGMII and RTBI interfaces can be operated at 2.5 V. The RGMII and RTBI interfaces follow the Reduced Gigabit Media-Independent Interface (RGMII) Specification Version 1.3. The RMII interface follows the RMII Consortium RMII Specification Version 1.2. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 22 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC) 8.1.1 MII, RMII, RGMII, and RTBI DC Electrical Characteristics MII and RMII drivers and receivers comply with the DC parametric attributes specified in Table 23 and Table 24. The RGMII and RTBI signals in Table 24 are based on a 2.5 V CMOS interface voltage as defined by JEDEC EIA/JESD8-5. Table 23. MII and RMII DC Electrical Characteristics Parameter Supply voltage 3.3 V Output high voltage (LVDD1/LVDD2 = Min, IOH = -4.0 mA) Output low voltage (LVDD1/LVDD2 = Min, IOL = 4.0 mA) Input high voltage Input low voltage Input high current (VIN = LVDD1, V IN = LVDD2) Input low current (VIN = GND) Note: 1. LVDD1 supports eTSEC 1. LVDD2 supports eTSEC 2. Symbol LV DD1 LV DD2 VOH VOL VIH VIL IIH IIL Min 3.13 2.40 GND 2.0 -0.3 -- -600 Max 3.47 LVDD1/LVDD2 + 0.3 0.50 LVDD1/LVDD2 + 0.3 0.90 30 -- Unit V V V V V A A -- -- -- -- -- Notes Table 24. RGMII and RTBI DC Electrical Characteristics Parameter Supply voltage 2.5 V Output high voltage (LVDD1/LVDD2 = Min, IOH = -1.0 mA) Output low voltage (LVDD1/LVDD2 = Min, IOL = 1.0 mA) Input high voltage Input low voltage Input high current (VIN = LVDD1, VIN = LVDD2) Input low current (VIN = GND) Note: 1 LV DD1 supports eTSEC 1. 2 LV DD2 supports eTSEC 2. Symbol LVDD1 LVDD2 VOH VOL VIH VIL IIH IIL Min 2.37 2.00 GND - 0.3 2.0 -0.3 -- -20 Max 2.63 LVDD1/LVDD2 + 0.3 0.40 LVDD1/LVDD2 + 0.3 0.70 -20 -- Unit V V V V V A A Notes 1, 2 -- -- -- -- 1, 2 -- MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 23 Ethernet: Enhanced Three-Speed Ethernet (eTSEC) 8.2 MII, RGMII, RMII, and RTBI AC Timing Specifications The AC timing specifications for MII, RGMII, RMII and RTBI are presented in this section. 8.2.1 MII AC Timing Specifications This section describes the MII transmit and receive AC timing specifications. 8.2.1.1 MII Transmit AC Timing Specifications Table 25. MII Transmit AC Timing Specifications Table 25 provides the MII transmit AC timing specifications. At recommended operating conditions with LVDD of 3.3 V 5%. Parameter TX_CLK clock period 10 Mbps TX_CLK clock period 100 Mbps TX_CLK duty cycle TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay TX_CLK data clock rise (20%-80%) TX_CLK data clock fall (80%-20%) Note: 1 Symbol 1 tMTX tMTX tMTXH/tMTX tMTKHDX tMTXR tMTXF Min -- -- 35 1 1.0 1.0 Typical 400 40 -- 5 -- -- Max -- -- 65 15 4.0 4.0 Unit ns ns % ns ns ns The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Figure 7 shows the MII transmit AC timing diagram. tMTX TX_CLK tMTXH TXD[3:0] TX_EN TX_ER tMTKHDX tMTXF tMTXR Figure 7. MII Transmit AC Timing Diagram MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 24 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC) 8.2.1.2 MII Receive AC Timing Specifications Table 26. MII Receive AC Timing Specifications Table 26 provides the MII receive AC timing specifications. At recommended operating conditions with LVDD of 3.3 V 5%. Parameter Input low voltage Input high voltage RX_CLK clock period 10 Mbps RX_CLK clock period 100 Mbps RX_CLK duty cycle RXD[3:0], RX_DV, RX_ER setup time to RX_CLK RXD[3:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise (20%-80%) RX_CLK clock fall time (80%-20%) Note: 1 Symbol 1 VIL VIH tMRX tMRX tMRXH/tMRX tMRDVKH tMRDXKH tMRXR tMRXF Min -- 1.9 -- -- 35 10.0 10.0 1.0 1.0 Typical -- -- 400 40 -- -- -- -- -- Max 0.7 -- -- -- 65 -- -- 4.0 4.0 Unit V V ns ns % ns ns ns ns The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Figure 8 provides the AC test load for eTSEC. Output Z0 = 50 LVDD/2 RL = 50 Figure 8. eTSEC AC Test Load MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 25 Ethernet: Enhanced Three-Speed Ethernet (eTSEC) Figure 9 shows the MII receive AC timing diagram. tMRX RX_CLK tMRXH RXD[3:0] RX_DV RX_ER tMRDVKH tMRDXKL tMRXF Valid Data tMRXR Figure 9. MII Receive AC Timing Diagram 8.2.2 RGMII and RTBI AC Timing Specifications Table 27. RGMII and RTBI AC Timing Specifications Table 27 presents the RGMII and RTBI AC timing specifications. At recommended operating conditions with LVDD of 2.5 V 5%. Parameter/Condition Data to clock output skew (at transmitter) Data to clock input skew (at receiver) Clock period Duty cycle for 1000Base-T Duty cycle for 10BASE-T and 100BASE-TX Rise time (20%-80%) Fall time (20%-80%) EC_GTX_CLK125 reference clock period EC_GTX_CLK125 reference clock duty cycle measured at 0.5 x LVDD1 1 Symbol1 tSKRGT tSKRGT tRGT tRGTH/tRGT tRGTH/tRGT tRGTR tRGTF tG12 tG125H/tG125 Min -600 1.0 7.2 45 40 -- -- -- 47 Typical 0 -- 8.0 50 50 -- -- 8.0 -- Max 600 2.8 8.8 55 60 0.75 0.75 -- 53 Unit ps ns ns % % ns ns ns % Notes -- 2 3 4 3, 4 -- -- 5 -- Note: Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII and RTBI timing. Note also that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT). 2 This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns will be added to the associated clock signal. 3 For 10 and 100 Mbps, t RGT scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 4 Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned between 5 This symbol represents the external EC_GTX_CLK125 and does not follow the original signal naming convention. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 26 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC) Figure 10 provides the AC test load for eTSEC. Output Z0 = 50 RL = 50 LVDD/2 Figure 10. eTSEC AC Test Load Figure 11 shows the RGMII and RTBI AC timing and multiplexing diagrams. tRGT tRGTH GTX_CLK (At Transmitter) tSKRGT TXD[8:5][3:0] TXD[7:4][3:0] TXD[8:5] TXD[3:0] TXD[7:4] TXD[4] TXEN TXD[9] TXERR tSKRGT TX_CLK (At PHY) TX_CTL RXD[8:5][3:0] RXD[7:4][3:0] RXD[8:5] RXD[3:0] RXD[7:4] tSKRGT RXD[4] RXDV RXD[9] RXERR tSKRGT RX_CTL RX_CLK (At PHY) Figure 11. RGMII and RTBI AC Timing and Multiplexing Diagrams MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 27 Ethernet: Enhanced Three-Speed Ethernet (eTSEC) 8.2.3 RMII AC Timing Specifications This section describes the RMII transmit and receive AC timing specifications. 8.2.3.1 RMII Transmit AC Timing Specifications Table 28. RMII Transmit AC Timing Specifications The RMII transmit AC timing specifications are in Table 28. At recommended operating conditions with LVDD of 3.3 V 5%. Parameter REF_CLK clock period REF_CLK duty cycle REF_CLK peak-to-peak jitter Rise time REF_CLK (20%-80%) Fall time REF_CLK (80%-20%) REF_CLK to RMII data TXD[1:0], TX_EN delay Symbol1 tRMT tRMTH tRMTJ tRMTR tRMTF tRMTDX Min 15.0 35 -- 1.0 1.0 2.0 Typical 20.0 50 -- -- -- -- Max 25.0 65 250 2.0 2.0 10.0 Unit ns % ps ns ns ns Note: 1 The symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Figure 12 shows the RMII transmit AC timing diagram. tRMT REF_CLK tRMTH TXD[1:0] TX_EN TX_ER tRMTDX tRMTF tRMTR Figure 12. RMII Transmit AC Timing Diagram MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 28 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC) 8.2.3.2 RMII Receive AC Timing Specifications Table 29. RMII Receive AC Timing Specifications Table 29 shows the RMII receive AC timing specifications. At recommended operating conditions with LVDD of 3.3 V 5%. Parameter/Condition Input low voltage at 3.3 LVDD Input high voltage at 3.3 LVDD REF_CLK clock period REF_CLK duty cycle REF_CLK peak-to-peak jitter Rise time REF_CLK (20%-80%) Fall time REF_CLK (80%-20%) RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK rising edge RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK rising edge Symbol1 VIL VIH tRMR tRMRH tRMRJ tRMRR tRMRF tRMRDV tRMRDX Min -- 2.0 15.0 35 -- 1.0 1.0 4.0 2.0 Typical -- -- 20.0 50 -- -- -- -- -- Max 0.8 -- 25.0 65 250 2.0 2.0 -- -- Unit V V ns % ps ns ns ns ns Note: 1 The symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Figure 13 provides the AC test load for eTSEC. Output Z0 = 50 LVDD/2 RL = 50 Figure 13. eTSEC AC Test Load MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 29 Ethernet: Enhanced Three-Speed Ethernet (eTSEC) Figure 14 shows the RMII receive AC timing diagram. tRMR REF_CLK tRMRH RXD[1:0] CRS_DV RX_ER tRMRDV tRMRDX tRMRF Valid Data tRMRR Figure 14. RMII Receive AC Timing Diagram 8.3 Management Interface Electrical Characteristics The electrical characteristics specified here apply to MII management interface signals MDIO (management data input/output) and MDC (management data clock). Figure 15 provides the AC test load for eTSEC. Output Z0 = 50 LVDD/2 RL = 50 Figure 15. eTSEC AC Test Load 8.3.1 MII Management DC Electrical Characteristics The MDC and MDIO are defined to operate at a supply voltage of 2.5 V or 3.3 V. The DC electrical characteristics for MDIO and MDC are provided in Table 30 and Table 31. Table 30. MII Management DC Electrical Characteristics When Powered at 2.5 V Parameter Supply voltage (2.5 V) Output high voltage Output low voltage Input high voltage Input low voltage Input high current Input low current IOH = -1.0 mA IOL = 1.0 mA -- -- Conditions -- LVDD1 = Min LVDD1 = Min LVDD1 = Min LVDD1 = Min VIN = LVDD1 VIN = LVDD1 Symbol LVDD1 VOH VOL VIH VIL IIH IIL Min 2.37 2.00 GND - 0.3 1.7 -0.3 -- -15 Max 2.63 LVDD1 + 0.3 0.40 -- 0.70 20 -- Unit V V V V V A A MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 30 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC) Table 31. MII Management DC Electrical Characteristics When Powered at 3.3 V Parameter Supply voltage (3.3 V) Output high voltage Output low voltage Input high voltage Input low voltage Input high current Input low current LVDD1 = Max LVDD1 = Max IOH = -1.0 mA IOL = 1.0 mA -- -- VIN 1 = 2.1 V VIN = 0.5 V Conditions -- LVDD1 = Min LVDD1 = Min Symbol LVDD1 VOH VOL VIH VIL IIH IIL Min 3.135 2.10 GND 2.00 -- -- -600 Max 3.465 LVDD1 + 0.3 0.50 -- 0.80 30 -- Unit V V V V V A A 8.3.2 MII Management AC Electrical Specifications Table 32. MII Management AC Timing Specifications Parameter Symbol 1 fMDC tMDC tMDCH tMDKHDV tMDKHDX tMDDVKH tMDDXKH tMDCR tMDCF Min 2.5 80 32 2 x (tplb_clk x 8) 10 5 0 -- -- -- -- -- -- -- Typical -- -- -- Max 8.3 400 -- -- 2 x (tplb_clk x 8) -- -- 10 10 Unit MHz ns ns ns ns ns ns ns ns Notes 2, 3 -- -- 5 3, 5 -- -- 4 4 Table 32 provides the MII management AC timing specifications. MDC frequency MDC period MDC clock pulse width high MDC to MDIO valid MDC to MDIO delay MDIO to MDC setup time MDIO to MDC hold time MDC rise time MDC fall time Note: 1 The symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2 This parameter is dependent on the system clock speed. (The maximum frequency is the maximum platform frequency divided by 64.) 3 This parameter is dependent on the system clock speed. (That is, for a system clock of 267 MHz, the maximum frequency is 8.3 MHz and the minimum frequency is 1.2 MHz; for a system clock of 375 MHz, the maximum frequency is 11.7 MHz and the minimum frequency is 1.7 MHz.) 4 Guaranteed by design. 5t plb_clk is the platform (CSB) clock divided according to the SCCR[TSEC1CM]. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 31 USB Figure 16 shows the MII management AC timing diagram. tMDC MDC tMDCH MDIO (Input) tMDDVKH tMDDXKH MDIO (Output) tMDKHDX tMDCF tMDCR Figure 16. MII Management Interface Timing Diagram 9 9.1 USB USB DC Electrical Characteristics This section provides the AC and DC electrical characteristics for the USB dual-role controllers. Table 33 provides the DC electrical characteristics for the USB interface at recommended OVDD = 3.3 V 165 mV. Table 33. USB DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage Input current High-level output voltage, IOH = -100 A Low-level output voltage, IOL = 100 A Symbol VIH VIL IIN VOH VOL Min 2 -0.3 -- OVDD - 0.2 -- Max OVDD + 0.3 0.8 30 -- 0.2 Unit V V A V V Note: The symbol VIN, in this case, represents the OVIN symbol referenced in Table 2. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 32 Freescale Semiconductor Local Bus 9.2 USB AC Electrical Specifications Table 34. USB General Timing Parameters (ULPI Mode Only) Parameter Symbol 1 tUSCK tUSIVKH tUSIXKH tUSKHOV tUSKHOX Min 15 4 1 -- 2 Max -- -- -- 7 -- Unit ns ns ns ns ns Table 34 describes the general timing parameters of the USB interface of the device. USB clock cycle time Input setup to USB clock--all inputs input hold to USB clock--all inputs USB clock to output valid--all outputs Output hold from USB clock--all outputs Figure 17 and Figure 18 provide the AC test load and signals for the USB, respectively. Output Z0 = 50 OVDD/2 RL = 50 Figure 17. USB AC Test Load USBDR_CLK tUSIVKH Input Signals tUSIXKH tUSKHOV Output Signals tUSKHOX Figure 18. USB Interface Timing Diagram 10 Local Bus This section describes the DC and AC electrical specifications for the local bus interface of the MPC8377E. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 33 Local Bus 10.1 Local Bus DC Electrical Characteristics Table 35. Local Bus DC Electrical Characteristics (LBVDD = 3.3 V) Table 35 and Table 36 provides the DC electrical characteristics for the local bus interface. At recommended operating conditions with LBVDD = 3.3 V. Parameter Supply voltage 3.3 V Output high voltage Output low voltage Input high voltage Input low voltage Input high current Input low current Conditions -- IOH = -4.0 mA IOL = 4.0 mA -- -- VIN 1 = LBVDD VIN 1 = GND LBVDD = Min LBVDD = Min -- -- Symbol LBVDD VOH VOL VIH VIL IIH IIL Min 3.135 2.40 -- 2.0 -0.3 -- -30 Max 3.465 -- 0.50 LBVDD + 0.3 0.90 30 -- Unit V V V V V A A Table 36. Local Bus DC Electrical Characteristics (LBVDD = 2.5 V) At recommended operating conditions with LBVDD = 2.5 V. Parameter Supply voltage 2.5 V Output high voltage Output low voltage Input high voltage Input low voltage Input high current Input low current Conditions -- IOH = -1.0 mA IOL = 1.0 mA -- -- VIN 1= Symbol LBVDD Min 2.37 2.00 -- 1.7 -0.3 -- -20 Max 2.73 -- 0.40 LBVDD + 0.3 0.70 20 -- Unit V V V V V A A LBV DD = Min LBV DD = Min LBV DD = Min LBV DD = Min LBVDD VOH VOL VIH VIL IIH IIL VIN 1 = GND Table 37. Local Bus DC Electrical Characteristics (LBVDD = 1.8 V) At recommended operating conditions with LBVDD = 1.8 V. Parameter Supply voltage 1.8 V Output high voltage Output low voltage Input high voltage Input low voltage Input high current Input low current Conditions -- IOH = -1.0 mA IOL = 1.0 mA -- -- LBVDD = Min LBVDD = Min LBVDD = Min LBVDD = Min VIN 1 = LBVDD VIN 1= Symbol LBVDD VOH VOL VIH VIL IIH IIL Min 1.71 LBVDD - 0.45 -- 0.65 x LBVDD -0.3 -- -10 Max 1.89 -- 0.45 LBVDD + 0.3 0.35 x LBVDD 10 -- Unit V V V V V A A GND MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 34 Freescale Semiconductor Local Bus 10.2 Local Bus AC Electrical Specifications Table 38. Local Bus General Timing Parameters--PLL Enable Mode Parameter Symbol 1 tLBK tLBIVKH tLBIXKH tLBIVKH1 tLBOTOT1 tLBOTOT2 tLBOTOT3 tLBKHLR tLBKHOV tLBKHOZ tLBKHOX Min 7.5 1.5 1.0 1.5 1.5 3 2.5 -- -- -- 1 Max 15 -- -- -- -- -- -- 4.5 4.5 3.8 -- Unit ns ns ns ns ns ns ns ns ns ns ns Notes 2 3, 4 3, 4 3, 4 5 6 7 -- 3 3, 8 3 Table 38 describes the general timing parameters of the local bus interface of the device. Local bus cycle time Input setup to local bus clock (except LUPWAIT/LGTA) Input hold from local bus clock LUPWAIT/LGTA input setup to local bus clock LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) Local bus clock to LALE rise Local bus clock to output valid (except LALE) Local bus clock to output high impedance for LAD/LDP Output hold from local bus clock for LAD/LDP Note: 1 The symbols used for timing specifications herein follow the pattern of t (First two letters of functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2 All timings are in reference to rising edge of LSYNC_IN at LBV /2 and the 0.4 LBV x DD DD of the signal in question. 3 All signals are measured from LBV /2 of the rising/falling edge of LSYNC_IN to 0.5 x LBV DD DD of the signal in question. 4 Input timings are measured at the pin. 5t LBOTOT1 should be used when LBCR[AHD] is not set and the load on LALE output pin is at least 10pF less than the load on LAD output pins. 6t LBOTOT2 should be used when LBCR[AHD] is set and the load on LALE output pin is at least 10pF less than the load on LAD output pins. 7t LBOTOT3 should be used when LBCR[AHD] is set and the load on LALE output pin equals to the load on LAD output pins. 8 For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 35 Local Bus Table 38 describes the general timing parameters of the local bus interface of the device. Table 39. Local Bus General Timing Parameters--PLL Bypass Mode Parameter Local bus cycle time Input setup to local bus clock Input hold from local bus clock LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) Local bus clock to output valid Local bus clock to output high impedance for LAD/LDP 1 Symbol1 tLBK tLBIVKH tLBIXKH tLBOTOT1 tLBOTOT2 tLBOTOT3 tLBKHOV tLBKHOZ Min 15 7.0 1.0 1.5 3.0 2.5 -- -- Max -- -- -- -- -- -- 3.0 4.0 Unit ns ns ns ns ns ns ns ns Notes 2 3, 4 3, 4 5 6 7 3 3, 8 Note: The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2 All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of LCLK0 (for all other inputs). 3 All signals are measured from LBV /2 of the rising/falling edge of LCLK0 to 0.4 x LBV DD DD of the signal in question for 3.3-V signaling levels. 4 Input timings are measured at the pin. 5t LBOTOT1 should be used when LBCR[AHD] is not set and the load on LALE output pin is at least 10pF less than the load on LAD output pins. 6t LBOTOT2 should be used when LBCR[AHD] is set and the load on LALE output pin is at least 10pF less than the load on LAD output pins. 7t LBOTOT3 should be used when LBCR[AHD] is set and the load on LALE output pin equals to the load on LAD output pins. 8 For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. Figure 19 provides the AC test load for the local bus. Output Z0 = 50 OVDD/2 RL = 50 Figure 19. Local Bus AC Test Load MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 36 Freescale Semiconductor Local Bus Figure 20 through Figure 25 show the local bus signals. LSYNC_IN tLBIVKH Input Signals: LAD[0:31]/LDP[0:3] tLBIVKH Input Signal: LGTA Output Signals: LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] LA[27:31]/LBCTL/LBCKE/LOE Output (Data) Signals: LAD[0:31]/LDP[0:3] tLBKHOV tLBKHOX tLBIXKH tLBIXKH tLBKHOV tLBKHOZ tLBKHOX Output (Address) Signal: LAD[0:31] tLBKHOV tLBKHOZ tLBKHOX LALE tLBKHLR tLBOTOT Figure 20. Local Bus Signals, Non-special Signals Only (PLL Enable Mode) MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 37 Local Bus LCLK[n] tLBIVKH Input Signals: LAD[0:15] tLBIVKH Input Signal: LGTA Output Signals: LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] LA[27:31]/LBCTL/LBCKE/LOE Output (Data) Signals: LAD[0:31]/LDP[0:3] tLBKHOV tLBIXKH tLBIXKH tLBKHOV tLBKHOZ Output (Address) Signal: LAD[0:31] tLBKHOV tLBKHOZ LALE tLBKHLR tLBOTOT Figure 21. Local Bus Signals, Non-special Signals Only (PLL Bypass Mode) MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 38 Freescale Semiconductor Local Bus LSYNC_IN T1 T3 tLBKHOV GPCM Mode Output Signals: LCS[0:7]/LWE[0:3] tLBIVKH UPM Mode Input Signal: LUPWAIT tLBIVKH tLBIXKH tLBIXKH tLBKHOX Input Signals: LAD[0:31]/LDP[0:3] tLBKHOX UPM Mode Output Signals: LCS[0:7]/LBS[0:1]/LGPL[0:5] tLBKHOV Output (Data) Signals: LAD[0:31]/LDP[0:3] tLBKHOV tLBKHOZ tLBKHOX Output (Address) Signal: LAD[0:31] tLBKHOV tLBKHOZ tLBKHOX Figure 22. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (PLL Enable Mode) MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 39 Local Bus LCLK T1 T3 tLBKHOV GPCM Mode Output Signals: LCS[0:7]/LWE[0:3] tLBIVKH UPM Mode Input Signal: LUPWAIT tLBIVKH tLBIXKH tLBIXKH tLBKHOZ Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:1]/LGPL[0:5] tLBKHOV tLBKHOZ Output (Data) Signals: LAD[0:31]/LDP[0:3] tLBKHOV Output (Address) Signal: LAD[0:31] tLBKHOV tLBKHOZ Figure 23. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (PLL Bypass Mode) MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 40 Freescale Semiconductor Local Bus LSYNC_IN T1 T2 T3 T4 tLBKHOV GPCM Mode Output Signals: LCS[0:7]/LWE[0:3] tLBIVKH UPM Mode Input Signal: LUPWAIT tLBIVKH tLBIXKH tLBIXKH tLBKHOZ Input Signals: LAD[0:31] tLBKHOX UPM Mode Output Signals: LCS[0:7]/LBS[0:1]/LGPL[0:5] tLBKHOV tLBKHOZ tLBKHOX Output (Data) Signals: LAD[0:31]/LDP[0:3] tLBKHOV tLBKHOZ tLBKHOX Output (Address) Signal: LAD[0:31] tLBKHOV Figure 24. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (PLL Enable Mode) MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 41 Enhanced Secure Digital Host Controller (eSDHC) LCLK T1 T2 T3 T4 tLBKHOV GPCM Mode Output Signals: LCS[0:7]/LWE[0:3] tLBIVKH UPM Mode Input Signal: LUPWAIT tLBIVKH tLBIXKH tLBIXKH tLBKHOZ Input Signals: LAD[0:31] tLBKHOV UPM Mode Output Signals: LCS[0:7]/LBS[0:1]/LGPL[0:5] tLBKHOV tLBKHOZ Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] tLBKHOV tLBKHOZ Figure 25. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (PLL Bypass Mode) 11 Enhanced Secure Digital Host Controller (eSDHC) This section describes the DC and AC electrical specifications for the eSDHC (SD/MMC) interface of the MPC8377E. The eSDHC controller always uses the falling edge of the SD_CLK in order to drive the SD_DAT[0:3]/CMD as outputs and sample the SD_DAT[0:3] as inputs. This behavior is true for both fulland high-speed modes. Note that this is a non-standard implementation, as the SD card specification assumes that in high-speed mode, that data will be driven at the rising edge of the clock. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 42 Freescale Semiconductor Enhanced Secure Digital Host Controller (eSDHC) Due to the special implementation of the eSDHC, there are constraints regarding the clock and data signals propagation delay on the user board. The constraints are for minimum and maximum delays, as well as skew between the CLK and DAT/CMD signals. In full speed mode, there is no need to add special delay on the data or clock signals. The user should make sure to meet the timing requirements as described further within this document. If the system is designed to support both high-speed and full-speed cards, the high-speed constraints should be fulfilled. If the systems is designed to operate up to 25 MHz only, full-speed mode is recommended. 11.1 eSDHC DC Electrical Characteristics Table 40. eSDHC interface DC Electrical Characteristics Parameter Symbol VIH VIL IIN VOH VOL Condition -- -- -- IOH = -100 uA, at OVDD(min) IOL = +100 uA, at OVDD(min) Min 0.625 x OVDD -0.3 -- 0.75 x OVDD -- Max OVDD + 0.3 0.25 x OV DD 30 -- 0.125 x OVDD Unit V V A V V Table 40 provides the DC electrical characteristics for the eSDHC (SD/MMC) interface of the device. Input high voltage Input low voltage Input current Output high voltage Output low voltage 11.2 eSDHC AC Timing Specifications (Full-Speed Mode) This section describes the AC electrical specifications for the eSDHC (SD/MMC) interface of the device. Table 41 provides the eSDHC AC timing specifications for full-speed mode as defined in Figure 27 and Figure 28. Table 41. eSDHC AC Timing Specifications for Full-Speed Mode At recommended operating conditions OVDD = 3.3 V 165 mV. Parameter SD_CLK clock frequency--full speed mode SD_CLK clock cycle SD_CLK clock frequency--identification mode SD_CLK clock low time SD_CLK clock high time SD_CLK clock rise and fall times Input setup times: SD_CMD, SD_DATx, SD_CD to SD_CLK Symbol 1 fSFSCK tSFSCK fSIDCK tSFSCKL tSFSCKH tSFSCKR/ tSFSCKF tSFSIVKH Min 0 40 0 15 15 -- 5 Max 25 -- 400 -- -- 5 -- Unit MHz ns KHz ns ns ns ns Notes -- -- -- 2 2 2 2 MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 43 Enhanced Secure Digital Host Controller (eSDHC) Table 41. eSDHC AC Timing Specifications for Full-Speed Mode (continued) At recommended operating conditions OVDD = 3.3 V 165 mV. Parameter Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK SD_CLK delay within device Output valid: SD_CLK to SD_CMD, SD_DATx valid Output hold: SD_CLK to SD_CMD, SD_DATx valid SD card input setup SD card input hold SD card output valid SD card output hold 1 Symbol 1 tSFSIXKH tINT_CLK_DLY tSFSKHOV tSFSKHOX tISU tIH tODLY tOH Min 0 1.5 -- 0 5 5 -- 0 Max -- -- 4 -- -- -- 14 -- Unit ns ns ns -- ns ns ns ns Notes 2 4 2 -- 3 3 3 3 Notes: The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state) for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSFSIXKH symbolizes eSDHC full mode speed device timing (SFS) input (I) to go invalid (X) with respect to the clock reference (K) going to high (H). Also tSFSKHOV symbolizes eSDHC full speed timing (SFS) for the clock reference (K) to go high (H), with respect to the output (O) going valid (V) or data output valid time. Note that, in general, the clock reference symbol representation is based on five letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2 Measured at capacitive load of 40 pF. 3 For reference only, according to the SD card specifications. 4 Average, for reference only. Figure 26 provides the eSDHC clock input timing diagram. eSDHC External Clock operational mode VM VM VM tSFSCKL tSFSCK VM = Midpoint Voltage (OVDD/2) tSFSCKR tSFSCKF tSFSCKH Figure 26. eSDHC Clock Input Timing Diagram MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 44 Freescale Semiconductor Enhanced Secure Digital Host Controller (eSDHC) 11.2.1 Full-Speed Output Path (Write) Figure 27 provides the data and command output timing diagram. tSFSCK (Clock Cycle) SD CLK at the MPC8377E Pin Driving Edge tCLK_DELAY SD CLK at the Card Pin Output Valid Time: tSFSKHOV Output Hold Time: tSFSKHOX Output from the MPC8377E Pins tSFSCKL Sampling Edge Input at the MPC8377E Pins tDATA_DELAY tISU (5 ns) tIH (5 ns) Figure 27. Full Speed Output Path 11.2.1.1 Full-Speed Write Meeting Setup (Maximum Delay) The following equations show how to calculate the allowed skew range between the SD_CLK and SD_DAT/CMD signals on the PCB. No clock delay: tSFSKHOV + tDATA_DELAY + tISU < tSFSCKL With clock delay: tSFSKHOV + tDATA_DELAY + tISU < tSFSCKL + tCLK_DELAY tDATA_DELAY + tSFSCKL < tSFSCK + tCLK_DELAY - tISU - tSFSKHOV This means that data can be delayed versus clock up to 11 ns in ideal case of tSFSCKL = 20 ns: tDATA_DELAY + 20 < 40 + tCLK_DELAY - 5 - 4 tDATA_DELAY < 11 + tCLK_DELAY 11.2.1.2 Full-Speed Write Meeting Hold (Minimum Delay) The following equations show how to calculate the allowed skew range between the SD_CLK and SD_DAT/CMD signals on the PCB. tCLK_DELAY < tSFSCKL + tSFSKHOX + tDATA_DELAY - tIH tCLK_DELAY + tIH - tSFSKHOX < tSFSCKL+ tDATA_DELAY MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 45 Enhanced Secure Digital Host Controller (eSDHC) This means that clock can be delayed versus data up to 15 ns (external delay line) in ideal case of tSFSCLKL = 20 ns: tCLK_DELAY + 5 - 0 < 20 + tDATA_DELAY tCLK_DELAY < 15 + tDATA_DELAY 11.2.1.3 Full-Speed Write Combined Formula The following equation is the combined formula to calculate the allowed skew range between the SD_CLK and SD_DAT/CMD signals on the PCB. tCLK_DELAY + tIH - tSFSKHOX < tSFSCKL + tDATA_DELAY < tSFSCK+ tCLK_DELAY - tISU - tSFSKHOV 11.2.2 Full-Speed Input Path (Read) Figure 28 provides the data and command input timing diagram. tSFSCK (Clock Cycle) SD CLK at the MPC8377E Pin tCLK_DELAY SD CLK at the Card Pin Driving Edge tODLY tOH Output from the SD Card Pins tDATA_DELAY Sampling Edge Input at the MPC8377E Pins (MPC8377E Input Hold) tSFSIXKH tSFSIVKH Figure 28. Full Speed Input Path 11.2.2.1 Full-Speed Read Meeting Setup (Maximum Delay) The following equations show how to calculate the allowed combined propagation delay range of the SD_CLK and SD_DAT/CMD signals on the PCB. tCLK_DELAY + tDATA_DELAY + tODLY + tSFSIVKH < tSFSCK tCLK_DELAY + tDATA_DELAY < tSFSCK - tODLY - tSFSIVKH - tINT_CLK_DLY 11.2.2.2 Full-Speed Read Meeting Hold (Minimum Delay) There is no minimum delay constraint due to the full clock cycle between the driving and sampling of data. tCLK_DELAY + tOH + tDATA_DELAY > tSFSIXKH MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 46 Freescale Semiconductor Enhanced Secure Digital Host Controller (eSDHC) This means that Data + Clock delay must be greater than -2 ns. This is always fulfilled. 11.3 eSDHC AC Timing Specifications (High-Speed Mode) Table 42 provides the eSDHC AC timing specifications for high-speed mode as defined in Figure 30 and Figure 31. Table 42. eSDHC AC Timing Specifications for High-Speed Mode At recommended operating conditions OVDD = 3.3 V 165 mV. Parameter SD_CLK clock frequency--high speed mode SD_CLK clock cycle SD_CLK clock frequency--identification mode SD_CLK clock low time SD_CLK clock high time SD_CLK clock rise and fall times Input setup times: SD_CMD, SD_DATx, SD_CD to SD_CLK Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK Output delay time: SD_CLK to SD_CMD, SD_DATx valid Output Hold time: SD_CLK to SD_CMD, SD_DATx invalid SD_CLK delay within device SD Card Input Setup SD Card Input Hold SD Card Output Valid SD Card Output Hold 1 Symbol1 fSHSCK tSFSCK fSIDCK tSHSCKL tSHSCKH tSHSCKR/ tSHSCKF tSHSIVKH tSHSIXKH tSHSKHOV tSHSKHOX tINT_CLK_DLY tISU tIH tODLY tOH Min 0 20 0 7 7 -- 5 0 -- 0 1.5 6 2 -- 2.5 Max 50 -- 400 -- -- 3 -- -- 4 -- -- -- -- 14 -- Unit MHz ns KHz ns ns ns ns ns ns ns ns ns ns ns ns Notes -- -- -- 2 2 2 2 2 2 2 4 3 3 3 3 Note: The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state) for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSFSIXKH symbolizes eSDHC full mode speed device timing (SFS) input (I) to go invalid (X) with respect to the clock reference (K) going to high (H). Also tSFSKHOV symbolizes eSDHC full speed timing (SFS) for the clock reference (K) to go high (H), with respect to the output (O) going valid (V) or data output valid time. Note that, in general, the clock reference symbol representation is based on five letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2 Measured at capacitive load of 40 pF. 3 For reference only, according to the SD card specifications. 4 Average, for reference only. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 47 Enhanced Secure Digital Host Controller (eSDHC) Figure 29 provides the eSDHC clock input timing diagram. eSDHC External Clock operational mode VM VM VM tSHSCKL tSHSCK VM = Midpoint Voltage (OVDD/2) tSHSCKR tSHSCKF tSHSCKH Figure 29. eSDHC Clock Input Timing Diagram 11.3.1 High-Speed Output Path (Write) Figure 30 provides the data and command output timing diagram. tSHSCK (Clock Cycle) SD CLK at the MPC8377E Pin Driving Edge tCLK_DELAY SD CLK at the Card Pin Output Valid Time: tSHSKHOV Output Hold Time: tSHSKHOX Output from the MPC8377E Pins tSHSCKL Sampling Edge Input at the SD Card Pins tDATA_DELAY tISU (6 ns) tIH (2 ns) Figure 30. High Speed Output Path 11.3.1.1 High-Speed Write Meeting Setup (Maximum Delay) The following equations show how to calculate the allowed skew range between the SD_CLK and SD_DAT/CMD signals on the PCB. Zero clock delay: tSHSKHOV + tDATA_DELAY + tISU < tSHSCKL With clock delay: tSHSKHOV + tDATA_DELAY + tISU < tSHSCKL + tCLK_DELAY tDATA_DELAY - tCLK_DELAY < tSHSCKL - tISU - tSHSKHOV MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 48 Freescale Semiconductor Enhanced Secure Digital Host Controller (eSDHC) This means that data delay should be equal or less than the clock delay in the ideal case where tSHSCLKL = 10 ns: tDATA_DELAY - tCLK_DELAY < 10 - 6 - 4 tDATA_DELAY - tCLK_DELAY < 0 11.3.1.2 High-Speed Write Meeting Hold (Minimum Delay) The following equations show how to calculate the allowed skew range between the SD_CLK and SD_DAT/CMD signals on the PCB. tCLK_DELAY < tSHSCKL + tSHSKHOX + tDATA_DELAY - tIH tCLK_DELAY - tDATA_DELAY < tSHSCKL + tSHSKHOX - tIH This means that clock can be delayed versus data up to 8 ns (external delay line) in ideal case of tSHSCLKL = 10 ns: tCLK_DELAY - tDATA_DELAY < 10 + 0 - 2 tCLK_DELAY - tDATA_DELAY < 8 11.3.2 High-Speed Input Path (Read) Figure 31 provides the data and command input timing diagram. tSHSCK (Clock Cycle) 1/2 Cycle SD CLK at the MPC8377E Pin tCLK_DELAY SD CLK at the Card Pin Driving Edge tODLY tOH Output from the SD Card Pins tDATA_DELAY Wrong Edge Right Edge Sampling Edge Input at the MPC8377E Pins tSHSIVKH (MPC8377E Input Setup) (MPC8377E Input Hold) tSHSIXKH Figure 31. High Speed Input Path For the input path, the device eSDHC expects to sample the data 1.5 internal clock cycles after it was driven by the SD card. Since in this mode the SD card drives the data at the rising edge of the clock, a sufficient delay to the clock and the data must exist to ensure it will not be sampled at the wrong internal clock falling edge. Note that the internal clock which is guaranteed to be 50% duty cycle is used to sample the data, and therefore used in the equations. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 49 JTAG 11.3.2.1 High-Speed Read Meeting Setup (Maximum Delay) The following equations show how to calculate the allowed combined propagation delay range of the SD_CLK and SD_DAT/CMD signals on the PCB. tCLK_DELAY + tDATA_DELAY + tODLY + tSHSIVKH < 1.5 x tSHSCK tCLK_DELAY + tDATA_DELAY < 1.5 x tSHSCK - tODLY - tSHSIVKH This means that Data + Clock delay can be up to 11 ns for a 20 ns clock cycle: tCLK_DELAY + tDATA_DELAY < 30 - 14 - 5 tCLK_DELAY + tDATA_DELAY < 11 11.3.2.2 High-Speed Read Meeting Hold (Minimum Delay) The following equations show how to calculate the allowed combined propagation delay range of the SD_CLK and SD_DAT/CMD signals on the PCB. 0.5 x tSHSCK < tCLK_DELAY + tDATA_DELAY + tOH - tSHSIXKH + tINT_CLK_DLY 0.5 x tSHSCK - tOH + tSHSIXKH - tINT_CLK_DLY < tCLK_DELAY + tDATA_DELAY This means that Data + Clock delay must be greater than ~6 ns for a 20 ns clock cycle: 10 - 2.5 + (-1.5) < tCLK_DELAY + tDATA_DELAY 6 < tCLK_DELAY + tDATA_DELAY 11.3.2.3 High-Speed Read Combined Formula The following equation is the combined formula to calculate the propagation delay range of the SD_CLK and SD_DAT/CMD signals on the PCB. 0.5 x tSHSCK - tOH + tSHSIXKH < tCLK_DELAY + tDATA_DELAY < 1.5 x tSHSCK - tODLY - tSHSIVKH 12 JTAG This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the MPC8377E. 12.1 JTAG DC Electrical Characteristics Table 43 provides the DC electrical characteristics for the IEEE 1149.1 (JTAG) interface of the MPC8377E. Table 43. JTAG interface DC Electrical Characteristics Parameter Input high voltage Input low voltage Input current Symbol VIH VIL IIN Condition -- -- -- Min 2.5 -0.3 -- Max OVDD + 0.3 0.8 30 Unit V V A MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 50 Freescale Semiconductor JTAG Table 43. JTAG interface DC Electrical Characteristics (continued) Parameter Output high voltage Output low voltage Output low voltage Symbol VOH VOL VOL Condition IOH = -8.0 mA IOL = 8.0 mA IOL = 3.2 mA Min 2.4 -- -- Max -- 0.5 0.4 Unit V V V 12.2 JTAG AC Timing Specifications This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the device. Table 44 provides the JTAG AC timing specifications as defined in Figure 33 through Figure 36. Table 44. JTAG AC Timing Specifications (Independent of CLKIN) 1 Parameter JTAG external clock frequency of operation JTAG external clock cycle time JTAG external clock pulse width measured at 1.4 V JTAG external clock rise and fall times TRST assert time Input setup times: Boundary-scan data TMS, TDI Input hold times: Boundary-scan data TMS, TDI Valid times: Boundary-scan data TDO Output hold times: Boundary-scan data TDO tJTKLDX tJTKLOX 2 2 -- -- tJTKLDV tJTKLOV 2 2 11 11 ns -- tJTDXKH tJTIXKH 10 10 -- -- ns -- tJTDVKH tJTIVKH 4 4 -- -- ns 4 Symbol2 fJTG t JTG tJTKHKL tJTGR & tJTGF tTRST Min 0 30 15 0 25 Max 33.3 -- -- 2 -- Unit MHz ns ns ns ns ns 4 Notes -- -- -- -- 3 MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 51 JTAG Table 44. JTAG AC Timing Specifications (Independent of CLKIN) 1 (continued) Parameter JTAG external clock to output high impedance: Boundary-scan data TDO Symbol2 Min Max Unit ns tJTKLDZ tJTKLOZ 2 2 19 9 5 Notes Notes: 1 All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50 load (see Figure 17). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2 The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 3 TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 4 Non-JTAG signal input timing with respect to t TCLK. 5 Non-JTAG signal output timing with respect to t TCLK. Figure 32 provides the AC test load for TDO and the boundary-scan outputs of the device. Output Z0 = 50 OVDD/2 R L = 50 Figure 32. AC Test Load for the JTAG Interface Figure 33 provides the JTAG clock input timing diagram. JTAG External Clock VM tJTKHKL tJTG VM = Midpoint Voltage (OVDD/2) VM VM tJTGR tJTGF Figure 33. JTAG Clock Input Timing Diagram Figure 34 provides the TRST timing diagram. TRST VM tTRST VM = Midpoint Voltage (OVDD/2) VM Figure 34. TRST Timing Diagram MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 52 Freescale Semiconductor JTAG Figure 35 provides the boundary-scan timing diagram. JTAG External Clock VM tJTDVKH tJTDXKH Boundary Data Inputs tJTKLDV tJTKLDX Boundary Data Outputs tJTKLDZ Boundary Data Outputs Output Data Valid VM = Midpoint Voltage (OVDD/2) Output Data Valid Input Data Valid VM Figure 35. Boundary-Scan Timing Diagram Figure 36 provides the test access port timing diagram. JTAG External Clock VM tJTIVKH tJTIXKH TDI, TMS tJTKLOV tJTKLOX TDO tJTKLOZ TDO Output Data Valid VM = Midpoint Voltage (OVDD/2) Output Data Valid Input Data Valid VM Figure 36. Test Access Port Timing Diagram MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 53 I2C 13 I2C This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8377E. 13.1 I2C DC Electrical Characteristics Table 45. I2C DC Electrical Characteristics Table 45 provides the DC electrical characteristics for the I2C interface of the MPC8377E. At recommended operating conditions with OVDD of 3.3 V 165 mV. Parameter Input high voltage level Input low voltage level Low level output voltage Output fall time from VIH(min) to VIL(max) with a bus capacitance from 10 to 400 pF Pulse width of spikes which must be suppressed by the input filter Capacitance for each I/O pin Input current (0 V VIN OVDD) 1 Symbol VIH VIL VOL tI2KLKV tI2KHKL CI IIN Min 0.7 x OVDD -0.3 0 20 + 0.1 x CB 0 -- -- Max OVDD + 0.3 0.3 x OVDD 0.2 x OVDD 250 50 10 30 Unit V V V ns ns pF A Notes -- -- 1 2 3 -- 4 Note: Output voltage (open drain or open collector) condition = 3 mA sink current. 2 C = capacitance of one bus line in pF. B 3 Refer to the MPC8379E PowerQUICC II Pro Integrated Host Processor Reference Manual for information on the digital filter used. 4 I/O pins will obstruct the SDA and SCL lines if OV DD is switched off. 13.2 I2C AC Electrical Specifications Table 46. I2C AC Electrical Specifications Table 46 provides the AC timing parameters for the I2C interface of the device. All values refer to VIH (min) and VIL (max) levels (see Table 45). Parameter SCL clock frequency Low period of the SCL clock High period of the SCL clock Setup time for a repeated START condition Hold time (repeated) START condition (after this period, the first clock pulse is generated) Data setup time Symbol1 fI2C tI2CL tI2CH tI2SVKH tI2SXKL tI2DVKH Min 0 1.3 0.6 0.6 0.6 100 Max 400 -- -- -- -- -- Unit kHz s s s s ns Notes -- -- -- -- -- -- MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 54 Freescale Semiconductor I2C Table 46. I2C AC Electrical Specifications (continued) All values refer to VIH (min) and VIL (max) levels (see Table 45). Parameter Data hold time CBUS compatible masters I2C bus devices Setup time for STOP condition Bus free time between a STOP and START condition Noise margin at the LOW level for each connected device (including hysteresis) Noise margin at the HIGH level for each connected device (including hysteresis) 1 Symbol1 tI2DXKL Min Max Unit s Notes 2, 3 -- 0 tI2PVKH tI2KHDX VNL VNH 0.6 1.3 0.1 x OVDD 0.2 x OVDD -- 0.9 -- -- -- -- s s V V -- -- -- -- Note: The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2 MPC8377E provides a hold time of at least 300 ns for the SDA signal (referred to the V IHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. 3 The maximum t I2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal. Figure 37 provides the AC test load for the I2C. Output Z0 = 50 OVDD/2 RL = 50 Figure 37. I2C AC Test Load Figure 38 shows the AC timing diagram for the I2C bus. SDA tI2CF tI2CL SCL tI2SXKL S tI2DXKL tI2CH Sr tI2SVKH tI2PVKH P S tI2DVKH tI2SXKL tI2KHKL tI2CR tI2CF Figure 38. I2C Bus AC Timing Diagram MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 55 PCI 14 PCI This section describes the DC and AC electrical specifications for the PCI bus of the MPC8377E. 14.1 PCI DC Electrical Characteristics Table 47 provides the DC electrical characteristics for the PCI interface of the device. The DC characteristics of the PORESET signal, which can be used as PCI RST in applications where the device is a PCI agent, deviates from the standard PCI levels. Table 47. PCI DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input current Condition VOUT VOH (min) or VOUT VOL (max) IOH = -500 A IOL = 1500 A 0 V VIN OVDD Symbol VIH VIL VOH VOL IIN Min 0.5 x OVDD -0.5 0.9 x OVDD -- -- Max OVDD + 0.5 0.3 x OVDD -- 0.1 x OVDD 30 Unit V V V V A Note: * The symbol VIN, in this case, represents the OVIN symbol referenced in Table 2. 14.2 PCI AC Electrical Specifications This section describes the general AC timing parameters of the PCI bus of the device. Note that the PCI_CLK/PCI_SYNC_IN or CLKIN signal is used as the PCI input clock depending on whether the MPC8377E is configured as a host or agent device. CLKIN is used when the device is in host mode. Table 48 shows the PCI AC timing specifications at 66 MHz. . Table 48. PCI AC Timing Specifications at 66 MHz Parameter Symbol1 tPCKHOV tPCKHOX tPCKHOZ tPCIVKH Min -- 1 -- 3.0 Max 6.0 -- 14 -- Unit ns ns ns ns Notes 2 2 2, 3 2, 4 PCI_SYNC_IN clock input levels are with next levels: VIL = 0.1xOVDD, VIH = 0.7xOVDD. Clock to output valid Output hold from Clock Clock to output high impedance Input setup to Clock MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 56 Freescale Semiconductor PCI Table 48. PCI AC Timing Specifications at 66 MHz (continued) PCI_SYNC_IN clock input levels are with next levels: VIL = 0.1xOVDD, VIH = 0.7xOVDD. Parameter Input hold from Clock Output Clock Skew Symbol1 tPCIXKH tPCKOSK Min 0.25 -- Max -- 0.5 Unit ns ns Notes 2, 4, 6 5 Notes: 1 Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state. 2 See the timing measurement conditions in the PCI 2.3 Local Bus Specifications. 3 For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4 Input timings are measured at the pin. 5 PCI specifications allows 1 ns skew for 66 MHz but includes the total allowed skew, board, connectors, etc. 6 Value does not comply with the PCI 2.3 Local Bus Specifications. Table 49 shows the PCI AC timing specifications at 33 MHz. Table 49. PCI AC Timing Specifications at 33 MHz PCI_SYNC_IN clock input levels are with next levels: VIL = 0.1 x OVDD, VIH = 0.7xOVDD. Parameter Clock to output valid Output hold from Clock Clock to output high impedance Input setup to Clock Input hold from Clock Output Clock skew Symbol1 tPCKHOV Min -- 2 -- 3.0 0.25 -- Max 11 -- 14 -- -- 0.5 Unit ns ns ns ns ns ns Notes 2 2 2, 3 2, 4 2, 4, 6 5 tPCKHOX tPCKHOZ tPCIVKH tPCIXKH tPCKOSK Note: 1 Note that the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state. 2 See the timing measurement conditions in the PCI 2.3 Local Bus Specifications. 3 For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4 Input timings are measured at the pin. 5 PCI specifications allows 2 ns skew for 33 MHz but includes the total allowed skew, board, connectors, etc. 6 Value does not comply with the PCI 2.3 Local Bus Specifications. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 57 PCI Express Figure 39 provides the AC test load for PCI. Output Z0 = 50 RL = 50 OVDD/2 Figure 39. PCI AC Test Load Figure 40 shows the PCI input AC timing conditions. CLK tPCIVKH tPCIXKH Input Figure 40. PCI Input AC Timing Measurement Conditions Figure 41 shows the PCI output AC timing conditions. CLK tPCKHOV Output Delay tPCKHOZ High-Impedance Output tPCKHOX Figure 41. PCI Output AC Timing Measurement Condition 15 PCI Express This section describes the DC and AC electrical specifications for the PCI Express bus. 15.1 DC Requirements for PCI Express SD_REF_CLK and SD_REF_CLK For more information see Section 21, "High-Speed Serial Interfaces (HSSI)." MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 58 Freescale Semiconductor PCI Express 15.2 AC Requirements for PCI Express SerDes Clocks Table 50. SD_REF_CLK and SD_REF_CLK AC Requirements Parameter Symbol tREF tREFCJ tREFPJ tCKCJ tCKPJ Min -- -- -50 -- -50 Typical 10 -- -- -- -- Max -- 100 +50 100 +50 Unit ns ps ps ps ps Notes -- -- -- -- 2, 3 Table 50 lists the PCI Express SerDes clock AC requirements. REFCLK cycle time REFCLK cycle-to-cycle jitter. Difference in the period of any two adjacent REFCLK cycles. REFCLK phase jitter peak-to-peak. Deviation in edge location with respect to mean edge location. SD_REF_CLK/_B cycle to cycle clock jitter (period jitter) SD_REF_CLK/_B phase jitter peak-to-peak. Deviation in edge location with respect to mean edge location. 1 Note: All options provide serial interface bit rate of 1.5 and 3.0 Gbps. 2 In a frequency band from 150 kHz to 15 MHz, at BER of 10-12. 3 Total peak-to-peak Deterministic Jitter "J " should be less than or equal to 50 ps. D 15.3 Clocking Dependencies The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all times. This is specified to allow bit rate clock sources with a 300 ppm tolerance. 15.4 Physical Layer Specifications Following is a summary of the specifications for the physical layer of PCI Express on this device. For further details as well as the specifications of the transport and data link layer please use the PCI Express Base Specification, Rev. 1.0a. NOTE The voltage levels of the transmitter and the receiver depend on the SerDes control registers which should be programmed at the recommended values for PCI Express protocol (that is, L1_nVDD = 1.0 V). MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 59 PCI Express 15.4.1 Differential Transmitter (Tx) Output Table 51 defines the specifications for the differential output at all transmitters. The parameters are specified at the component pins. Table 51. Differential Transmitter (Tx) Output Specifications Parameter Unit interval Conditions Each UPETX is 400 ps 300 ppm. UPETX does not account for Spread Spectrum Clock dictated variations. VPEDPPTX = 2 x |V TX-D+ - VTX-D-| Ratio of the VPEDPPTX of the second and following bits after a transition divided by the VPEDPPTX of the first bit after a transition. The maximum Transmitter jitter can be derived as TTX-MAX-JITTER = 1 - UPEEWTX= 0.3 UI. Jitter is defined as the measurement variation of the crossing points (V PEDPPTX = 0 V) in relation to a recovered TX UI. A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI. -- Symbol UI Min 399.88 Typical 400 Max 400.12 Units ps Notes 1 Differential peak-to-peak output voltage De-emphasized differential output voltage (ratio) VTX-DIFFp-p 0.8 -- 1.2 V 2 VTX-DE-RATIO -3.0 -3.5 -4.0 dB 2 Minimum Tx eye width TTX-EYE 0.70 -- -- UI 2, 3 Maximum time between the jitter median and maximum deviation from the median TTX-EYE-MEDIAN-toMAX-JITTER -- -- 0.15 UI 2, 3 D+/D- Tx output rise/fall time TTX-RISE, T TX-FALL VTX-CM-ACp 0.125 -- -- -- -- 20 UI mV 2, 5 2 RMS AC peak common VPEACPCMTX = RMS(|VTXD+ - mode output voltage VTXD-|/2 - VTX-CM-DC) VTX-CM-DC = DC(avg) of |VTX-D+ - VTX-D-|/2 Absolute delta of DC common mode voltage during LO and electrical idle |VTX-CM-DC (during LO) - VTX-CM-Idle-DC (During Electrical Idle)|<=100 mV VTX-CM-DC = DC(avg) of |VTX-D+ - VTX-D-|/2 [LO] VTX-CM-Idle-DC = DC(avg) of |VTX-D+ - VTX-D-|/2 [Electrical Idle] VTX-CM-DC- ACTIVEIDLE-DELTA 0 -- 100 mV 2 MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 60 Freescale Semiconductor PCI Express Table 51. Differential Transmitter (Tx) Output Specifications (continued) Parameter Absolute delta of DC common mode between D+ and D- Conditions |VTX-CM-DC-D+ - VTX-CM-DC-D-| 25 mV VTX-CM-DC-D+ = DC(avg) of |VTX-D+| VTX-CM-DC-D- = DC(avg) of |VTX-D-| Symbol VTX-CM-DC-LINEDELTA Min 0 Typical -- Max 25 Units mV Notes 2 VPEEIDPTX = |V TX-IDLE-D+ Electrical idle differential peak output -V TX-IDLE-D-| 20 mV voltage The total amount of voltage Amount of voltage change allowed during change that a transmitter can apply to sense whether a low receiver detection impedance receiver is present. Tx DC common mode voltage The allowed DC common mode voltage under any conditions. VTX-IDLE-DIFFp 0 -- 20 mV 2 VTX-RCV-DETECT -- XPADVDD/2 600 mV 6 VTX-DC-CM 0 XPADVDD/2 -- V 6 Tx short circuit current The total current the limit transmitter can provide when shorted to its ground Minimum time spent in Minimum time a transmitter electrical idle must be in electrical idle. Utilized by the receiver to start looking for an electrical idle exit after successfully receiving an electrical idle ordered set. Maximum time to transition to a valid electrical idle after sending an electrical idle ordered set ITX-SHORT -- -- 90 mA -- TTX-IDLE-MIN 50 -- -- UI -- After sending an electrical idle TTX-IDLE-SET-TO-IDLE ordered set, the transmitter must meet all electrical idle specifications within this time. This is considered a debounce time for the transmitter to meet electrical idle after transitioning from LO. Maximum time to meet all Tx TTX-IDLE-TO-DIFF-DATA specifications when transitioning from electrical idle to sending differential data. This is considered a debounce time for the Tx to meet all Tx specifications after leaving electrical idle Measured over 50 MHz to 1.25 GHz. RLTX-DIFF -- -- 20 UI -- Maximum time to transition to valid Tx specifications after leaving an electrical idle condition -- -- 20 UI -- Differential return loss 12 -- -- dB 4 MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 61 PCI Express Table 51. Differential Transmitter (Tx) Output Specifications (continued) Parameter Common mode return loss DC differential Tx impedance Transmitter DC impedance Lane-to-Lane output skew AC coupling capacitor Conditions Measured over 50 MHz to 1.25 GHz. Tx DC differential mode low impedance Required Tx D+ as well as D- DC impedance during all states Static skew between any two transmitter lanes within a single link All transmitters should be AC coupled. The AC coupling is required either within the media or within the transmitting component itself. This random timeout helps resolve conflicts in crosslink configuration by eventually resulting in only one downstream and one upstream port. Symbol RLTX-CM ZTX-DIFF-DC ZTX-DC Min 6 80 40 Typical -- 100 -- Max -- 120 -- Units dB Notes 4 -- -- LTX-SKEW -- -- 500 + 2 UI 200 ps -- CTX 75 -- nF -- Crosslink random timeout Tcrosslink 0 -- 1 ms 7 Note: No test load is necessarily associated with this value. 2 Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 44 and measured over any 250 consecutive Tx UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 42.) 3 AT TX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.30 UI for the transmitter collected over any 250 consecutive Tx UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total Tx jitter budget collected over any 250 consecutive Tx UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. 4 The transmitter input impedance will result in a differential return loss greater than or equal to 12 dB and a common mode return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for return loss measurements is 50 to ground for both the D+ and D- line (that is, as measured by a vector network analyzer with 50- probes, see Figure 44). Note that the series capacitors, CTX, is optional for the return loss measurement. 5 Measured between 20%-80% at transmitter package pins into a test load as shown in Figure 44 for both V TX-D+ and VTX-D-. 6 See Section 4.3.1.8 of the PCI Express Base Specifications, Rev 1.0a. 7 See Section 4.2.6.3 of the PCI Express Base Specifications, Rev 1.0a. 1 15.4.2 Transmitter Compliance Eye Diagrams The Tx eye diagram in Figure 42 is specified using the passive compliance/test measurement load (see Figure 44) in place of any real PCI Express interconnect + Rx component. There are two eye diagrams that must be met for the transmitter. Both diagrams must be aligned in time using the jitter median to locate the center of the eye diagram. The different eye diagrams differ in voltage depending on whether it is a MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 62 Freescale Semiconductor PCI Express transition bit or a de-emphasized bit. The exact reduced voltage level of the de-emphasized bit is always relative to the transition bit. The eye diagram must be valid for any 250 consecutive UIs. A recovered Tx UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the Tx UI. NOTE It is recommended that the recovered Tx UI be calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using a minimization merit function (that is, least squares and median deviation fits). V TX-DIFF = 0 mV (D+ D- Crossing Point) [Transition Bit] VTX-DIFFp-p-MIN = 800 mV V TX-DIFF = 0 mV (D+ D- Crossing Point) [De-emphasized Bit] 566 mV (3 dB) >= V TX-DIFFp-p-MIN >= 505 mV (4 dB) 0.7 UI = UI - 0.3 UI(JTX-TOTAL-MAX ) [Transition Bit] VTX-DIFFp-p-MIN = 800 mV Figure 42. Minimum Transmitter Timing and Voltage Output Compliance Specifications 15.4.3 Differential Receiver (Rx) Input Specifications Table 52 defines the specifications for the differential input at all receivers. The parameters are specified at the component pins. Table 52. Differential Receiver (Rx) Input Specifications Parameter Unit interval Comments Each U PERX is 400 ps 300 ppm. U PERX does not account for Spread Spectrum Clock dictated variations. VPEDPPRX = 2 x |V RX-D+ - VRX-D-| Symbol UI Min 399.88 Typical 400 Max 400.12 Units ps Notes 1 Differential peak-to-peak output voltage VRX-DIFFp-p 0.175 -- 1.200 V 2 MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 63 PCI Express Table 52. Differential Receiver (Rx) Input Specifications (continued) Parameter Minimum receiver eye width Comments The maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived as TRX-MAX-JITTER = 1 - UPEEWRX = 0.6 UI. Symbol TRX-EYE Min 0.4 Typical -- Max -- Units UI Notes 2, 3 Maximum time between the jitter median and maximum deviation from the median. Jitter is defined as the TRX-EYE-MEDIAN-to measurement variation of the -MAX-JITTER crossing points (VPEDPPRX = 0 V) in relation to a recovered Tx UI. A recovered Tx UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the Tx UI. VPEACPCMRX = |VRXD+ - VRXD-|/2 - VRX-CM-DC VRX-CM-DC = DC(avg) of |VRX-D+ - VRX-D-|/2 Measured over 50 MHz to 1.25 GHz with the D+ and D- lines biased at +300 mV and -300 mV, respectively. Measured over 50 MHz to 1.25 GHz with the D+ and D- lines biased at 0 V. RX DC differential mode impedance. Required RX D+ as well as DDC impedance (50 20% tolerance). Required RX D+ as well as D- DC impedance when the receiver terminations do not have power. VPEEIDT = 2 x |V RX-D+ -VRX-D-| Measured at the package pins of the receiver VRX-CM-ACp -- -- 0.3 UI 2, 3, 7 AC peak common mode input voltage -- -- 150 mV 2 Differential return loss RLRX-DIFF 10 -- -- dB 4 Common mode return loss DC differential input impedance DC Input Impedance RLRX-CM 6 -- -- dB 4 ZRX-DIFF-DC ZRX-DC 80 40 100 50 120 60 5 2, 5 Powered down DC input impedance ZRX-HIGH-IMP-DC 200 k -- -- 6 Electrical idle detect threshold VRX-IDLE-DET-DIFF p-p 65 -- 175 mV -- MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 64 Freescale Semiconductor PCI Express Table 52. Differential Receiver (Rx) Input Specifications (continued) Parameter Comments Symbol TRX-IDLE-DET-DIFFENTERTIME Min -- Typical -- Max 10 Units ms Notes -- Unexpected Electrical Idle An unexpected electrical idle (Vrx-diffp-p < Enter Detect Threshold Vrx-idle-det-diffp-p) must be Integration Time recognized no longer than Trx-idle-det-diff-entertime to signal an unexpected idle condition. Total Skew Skew across all lanes on a link. This includes variation in the length of SKP ordered set (e.g. COM and one to five SKP Symbols) at the Rx as well as any delay differences arising from the interconnect itself. LRX-SKEW -- -- 20 ns -- Note: No test load is necessarily associated with this value. 2 Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 44 should be used as the Rx device when taking measurements (also refer to the receiver compliance eye diagram shown in Figure 43). If the clocks to the Rx and Tx are not derived from the same reference clock, the Tx UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram. 3 AT Rx-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and interconnect collected any 250 consecutive UIs. The TRx-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any 250 consecutive Tx UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the Rx and Tx are not derived from the same reference clock, the Tx UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram. 4 The receiver input impedance will result in a differential return loss greater than or equal to 10 dB with the D+ line biased to 300 mV and the D- line biased to -300 mV and a common mode return loss greater than or equal to 6 dB (no bias required) over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for return loss measurements for is 50 to ground for both the D+ and D- line (that is, as measured by a vector network analyzer with 50- probes, see Figure 44). Note that the series capacitors, CTx, is optional for the return loss measurement. 5 Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM) there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port. 6 The Rx DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at 300 mV above the Rx ground. 7 It is recommended that the recovered Tx UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated data. 1 15.5 Receiver Compliance Eye Diagrams The Rx eye diagram in Figure 43 is specified using the passive compliance/test measurement load (see Figure 44) in place of any real PCI Express Rx component. In general, the minimum receiver eye diagram measured with the compliance/test measurement load (see Figure 44) is larger than the minimum receiver eye diagram measured over a range of systems at the input receiver of any real PCI Express component. The degraded eye diagram at the input receiver is due to traces internal to the package as well as silicon MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 65 PCI Express parasitic characteristics that cause the real PCI Express component to vary in impedance from the compliance/test measurement load. The input receiver eye diagram is implementation specific and is not specified. Rx component designer should provide additional margin to adequately compensate for the degraded minimum receiver eye diagram (shown in Figure 43) expected at the input receiver based on an adequate combination of system simulations and the return loss measured looking into the Rx package and silicon. The Rx eye diagram must be aligned in time using the jitter median to locate the center of the eye diagram. The eye diagram must be valid for any 250 consecutive UIs. A recovered Tx UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the Tx UI. NOTE The reference impedance for return loss measurements is 50. to ground for both the D+ and D- line (that is, as measured by a Vector Network Analyzer with 50. probes--see Figure 44). Note that the series capacitors, CPEACCTX, are optional for the return loss measurement. VRX-DIFF = 0 mV (D+ D- Crossing Point) VRX-DIFF = 0 mV (D+ D- Crossing Point) VRX-DIFFp-p-MIN > 175 mV 0.4 UI = TRX-EYE-MIN Figure 43. Minimum Receiver Eye Timing and Voltage Compliance Specification MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 66 Freescale Semiconductor Serial ATA (SATA) 15.5.1 Compliance Test and Measurement Load The AC timing and voltage parameters must be verified at the measurement point, as specified within 0.2 inches of the package pins, into a test/measurement load shown in Figure 44. NOTE The allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may benefit from D+ and D- not being exactly matched in length at the package pin boundary. If the vendor does not explicitly state where the measurement point is located, the measurement point is assumed to be the D+ and D- package pins. D+ Package Pin C = CTX TX Silicon + Package C = CTX D- Package Pin R = 50 R = 50 Figure 44. Compliance Test/Measurement Load 16 Serial ATA (SATA) This section describes the DC and AC electrical specifications for the serial ATA (SATA) of the MPC8377E. Note that the external cabled applications or long backplane applications (Gen1x and Gen2x) are not supported. 16.1 Requirements for SATA REF_CLK The reference clock is a single ended input clock required for the SATA interface operation. The AC requirements for the SATA reference clock are listed in the Table 53. Table 53. SATA Reference Clock Input Requirements Parameter SD_REF_CLK/ SD_REF_CLK frequency range SD_REF_CLK/ SD_REF_CLK clock frequency tolerance Condition -- Symbol tCLK_REF tCLK_TOL Min -- Typical 100/125/150 Max -- Unit MHz Notes 1 -- -350 0 +350 ppm -- SD_REF_CLK/ SD_REF_CLK reference clock duty cycle Measured at 1.6V tCLK_DUTY 40 50 60 % -- MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 67 Serial ATA (SATA) Table 53. SATA Reference Clock Input Requirements (continued) Parameter SD_REF_CLK/ SD_REF_CLK cycle to cycle Clock jitter (period jitter) SD_REF_CLK/ SD_REF_CLK total reference clock jitter, phase jitter (peak-peak) 1 Condition Cycle-to-cycle at ref clock input Symbol tCLK_CJ Min -- Typical -- Max 100 Unit ps Notes -- Peak-to-peak jitter at ref clock input tCLK_PJ -50 -- +50 ps 2, 3 Note: Only 100/125/150 MHz have been tested, othe in between values will not work correctly with the rest of the system. 2 In a frequency band from 150 kHz to 15 MHz at BER of 10-12. 3 Total peak to peak Deterministic Jitter "DJ" should be less than or equal to 50 ps. Figure 45 shows the SATA reference clock timing waveform. TH Ref_CLK TL Figure 45. SATA Reference Clock Timing Waveform 16.2 Transmitter (Tx) Output Characteristics This section discusses the Gen1i/1.5G and Gen2i/3G transmitter output characteristics for the SATA interface. 16.2.1 Gen1i/1.5G Transmitter Specifications Table 54 provides the DC differential transmitter output DC characteristics for the SATA interface at Gen1i or 1.5 Gbits/s transmission. Table 54. Gen1i/1.5G Transmitter (Tx) DC Specifications Parameter Tx differential output voltage Tx differential pair impedance 1 Symbol VSATA_TXDIFF ZSATA_TXDIFFIM Min 400 85 Typical 500 100 Max 600 115 Units mVp-p Notes 1 -- Note: Terminated by 50 load. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 68 Freescale Semiconductor Serial ATA (SATA) Table 55 provides the differential transmitter output AC characteristics for the SATA interface at Gen1i or 1.5 Gbits/s transmission. Table 55. Gen1i/1.5G Transmitter AC Specifications Parameter Channel speed Unit interval Total jitter, data-data 5 UI Total jitter, data-data 250 UI Deterministic jitter, data-data 5 UI Deterministic jitter, data-data 250 UI 1 Symbol tCH_SPEED TUI USATA_TXTJ5UI USATA_TXTJ250UI USATA_TXDJ5UI USATA_TXDJ250UI Min -- 666.4333 -- -- -- -- Typical 1.5 666.667 -- -- -- -- Max -- 670.2333 0.355 0.47 0.175 0.22 Units Gbps ps UIp-p UIp-p UIp-p UIp-p Notes -- -- 1 1 1 1 Note: Measured at Tx output pins peak to peak phase variation, random data pattern. 16.2.2 Gen2i/3G Transmitter Specifications Table 56 provides the differential transmitter output DC characteristics for the SATA interface at Gen2i or 3.0 Gbits/s transmission. Table 56. Gen 2i/3G Transmitter DC Specifications Parameter Tx differential output voltage Tx differential pair impedance Note: 1 Terminated by 50 load. Symbol VSATA_TXDIFF ZSATA_TXDIFFIM Min 400 85 Typical 550 100 Max 700 115 Units mVp-p Notes 1 -- Table 57 provides the differential transmitter output AC characteristics for the SATA interface at Gen2i or 3.0 Gbits/s transmission. Table 57. Gen 2i/3G Transmitter AC Specifications Parameter Channel speed Unit interval Total jitter fC3dB=fBAUD/10 Total jitter fC3dB = fBAUD/500 Symbol tCH_SPEED TUI USATA_TXTJfB/10 USATA_TXTJfB/500 Min -- 333.2 -- -- Typical 3.0 333.33 -- -- Max -- 335.11 0.3 0.37 Units Gbps ps UIp-p UIp-p Notes -- -- 1 1 MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 69 Serial ATA (SATA) Table 57. Gen 2i/3G Transmitter AC Specifications (continued) Parameter Total jitter fC3dB = fBAUD/1667 Deterministic jitter fC3dB = fBAUD/10 Deterministic jitter fC3dB = fBAUD/500 Deterministic jitter fC3dB = fBAUD/1667 Symbol USATA_TXTJfB/1667 USATA_TXDJfB/10 USATA_TXDJfB/500 USATA_TXDJfB/1667 Min -- -- -- -- Typical -- -- -- -- Max 0.55 0.17 0.19 0.35 Units UIp-p UIp-p UIp-p UIp-p Notes 1 1 1 1 Note: 1 Measured at Tx output pins peak to peak phase variation, random data pattern. 16.3 Differential Receiver (Rx) Input Characteristics This section discusses the Gen1i/1.5G and Gen2i/3G differential receiver input AC characteristics. 16.3.1 Gen1i/1.5G Receiver Specifications Table 58 provides the Gen1i or 1.5 Gbits/s differential receiver input DC characteristics for the SATA interface. Table 58. Gen1i/1.5G Receiver Input DC Specifications Parameter Differential input voltage Differential Rx input impedance Symbol VSATA_RXDIFF ZSATA_RXSEIM Min 240 85 Typical 500 100 Max 600 115 Units mVp-p Notes 1 -- Note: 1 Voltage relative to common of either signal comprising a differential pair. Table 59 provides the Gen1i or 1.5 Gbits/s differential receiver input AC characteristics for the SATA interface. Table 59. Gen 1i/1.5G Receiver AC Specifications Parameter Unit interval Total jitter, data-data 5 UI Total jitter, data-data 250 UI Deterministic jitter, data-data 5 UI Symbol TUI USATA_TXTJ5UI USATA_TXTJ250UI USATA_TXDJ5UI Min 666.4333 -- -- -- Typical 666.667 -- -- -- Max 670.2333 0.43 0.60 0.25 Units ps UIp-p UIp-p UIp-p Notes -- 1 1 1 MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 70 Freescale Semiconductor Serial ATA (SATA) Table 59. Gen 1i/1.5G Receiver AC Specifications (continued) Parameter Deterministic jitter, data-data 250 UI 1 Symbol USATA_TXDJ250UI Min -- Typical -- Max 0.35 Units UIp-p Notes 1 Note: Measured at Tx output pins peak to peak phase variation, random data pattern. 16.3.2 Gen2i/3G Receiver (Rx) Specifications Table 60 provides the Gen2i or 3 Gbits/s differential receiver input DC characteristics for the SATA interface. Table 60. Gen2i/3G Receiver Input DC Specifications Parameter Differential input voltage Differential RX input impedance 1 Symbol VSATA_RXDIFF ZSATA_RXSEIM Min 275 85 Typical 500 100 Max 750 115 Units mVp-p Notes 1 -- Note: Voltage relative to common of either signal comprising a differential pair. Table 61 provides the differential receiver output AC characteristics for the SATA interface at Gen2i or 3.0 Gbits/s transmission. Table 61. Gen 2i/3G Receiver AC Specifications Parameter Channel Speed Unit Interval Total jitter fC3dB = fBAUD/10 Total jitter fC3dB = fBAUD/500 Total jitter fC3dB = fBAUD/1667 Deterministic jitter fC3dB = fBAUD/10 Deterministic jitter fC3dB = fBAUD/500 Deterministic jitter fC3dB = fBAUD/1667 Symbol tCH_SPEED TUI USATA_TXTJfB/10 USATA_TXTJfB/500 USATA_TXTJfB/1667 USATA_TXDJfB/10 USATA_TXDJfB/500 USATA_TXDJfB/1667 Min -- 333.2 -- -- -- -- -- -- Typical 3.0 333.33 -- -- -- -- -- -- Max -- 335.11 0.46 0.60 0.65 0.35 0.42 0.35 Units Gbps ps UIp-p UIp-p UIp-p UIp-p UIp-p UIp-p Notes -- -- 1 1 1 1 1 1 Note: 1 Measured at Tx output pins peak to peak phase variation, random data pattern. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 71 Timers 17 Timers This section describes the DC and AC electrical specifications for the timers of the MPC8377E. 17.1 Timers DC Electrical Characteristics Table 62 provides the DC electrical characteristics for the device timers pins, including TIN, TOUT, TGATE, and RTC_CLK. Table 62. Timers DC Electrical Characteristics Parameter Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current Condition IOH = -6.0 mA IOL = 6.0 mA IOL = 3.2 mA -- -- 0 V VIN OVDD Symbol VOH VOL VOL VIH VIL IIN Min 2.4 -- -- 2.0 -0.3 -- Max -- 0.5 0.4 OVDD + 0.3 0.8 30 Unit V V V V V A 17.2 Timers AC Timing Specifications Table 63. Timers Input AC Timing Specifications 1 Parameter Symbol 2 tTIWID Min 20 Unit ns Table 63 provides the timers input and output AC timing specifications. Timers inputs--minimum pulse width Note: 1 Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin. 2 Timers inputs and outputs are asynchronous to any visible clock. Timers outputs should be synchronized before use by any external synchronous logic. Timers inputs are required to be valid for at least tTIWID ns to ensure proper operation Figure 46 provides the AC test load for the timers. Output Z0 = 50 OVDD/2 RL = 50 Figure 46. Timers AC Test Load MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 72 Freescale Semiconductor GPIO 18 GPIO This section describes the DC and AC electrical specifications for the GPIO of the MPC8377E. 18.1 GPIO DC Electrical Characteristics Table 64. GPIO DC Electrical Characteristics Table 64 provides the DC electrical characteristics for the device GPIO. This specification applies when operating at 3.3 V 165 mV supply. Parameter Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current Condition IOH = -6.0 mA IOL = 6.0 mA IOL = 3.2 mA -- -- 0 V VIN OVDD Symbol VOH VOL VOL VIH VIL IIN Min 2.4 -- -- 2.0 -0.3 -- Max -- 0.5 0.4 OVDD + 0.3 0.8 30 Unit V V V V V A 18.2 GPIO AC Timing Specifications Table 65. GPIO Input AC Timing Specifications Parameter Symbol tPIWID Min 20 Unit ns Table 65 provides the GPIO input and output AC timing specifications. GPIO inputs--minimum pulse width Note: 1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of SYS_CLKIN. Timings are measured at the pin. 2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any external synchronous logic. GPIO inputs are required to be valid for at least tPIWID ns to ensure proper operation. Figure 47 provides the AC test load for the GPIO. Output Z0 = 50 OVDD/2 RL = 50 Figure 47. GPIO AC Test Load 19 IPIC This section describes the DC and AC electrical specifications for the external interrupt pins of the MPC8377E. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 73 SPI 19.1 IPIC DC Electrical Characteristics Table 66. IPIC DC Electrical Characteristics Parameter Condition -- -- -- IOL = 6.0 mA IOL = 3.2 mA Symbol VIH VIL IIN VOL VOL Min 2.0 -0.3 -- -- -- Max OVDD + 0.3 0.8 30 0.5 0.4 Unit V V A V V Table 66 provides the DC electrical characteristics for the external interrupt pins of the MPC8377E. Input high voltage Input low voltage Input current Output low voltage Output low voltage Note: 1. This table applies for pins IRQ[0:7], IRQ_OUT, MCP_OUT. 2. IRQ_OUT and MCP_OUT are open drain pins, thus VOH is not relevant for those pins. 19.2 IPIC AC Timing Specifications Table 67. IPIC Input AC Timing Specifications Parameter Symbol tPIWID Min 20 Unit ns Table 67 provides the IPIC input and output AC timing specifications. IPIC inputs--minimum pulse width Note: 1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin. 2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any external synchronous logic. IPIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when working in edge triggered mode. 20 SPI This section describes the DC and AC electrical specifications for the SPI of the MPC8377E. 20.1 SPI DC Electrical Characteristics Table 68. SPI DC Electrical Characteristics Parameter Condition -- -- -- IOH = -8.0 mA Symbol VIH VIL IIN VOH Min 2.0 -0.3 -- 2.4 Max OVDD + 0.3 0.8 30 -- Unit V V A V Table 68 provides the DC electrical characteristics for the device SPI. Input high voltage Input low voltage Input current Output high voltage MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 74 Freescale Semiconductor SPI Table 68. SPI DC Electrical Characteristics (continued) Parameter Output low voltage Output low voltage Condition IOL = 8.0 mA IOL = 3.2 mA Symbol VOL VOL Min -- -- Max 0.5 0.4 Unit V V 20.2 SPI AC Timing Specifications Table 69. SPI AC Timing Specifications Parameter Symbol1 tNIKHOV tNEKHOV tNIIVKH tNIIXKH tNEIVKH tNEIXKH Min 0.5 2 4 0 4 2 Max 6 8 -- -- -- -- Unit ns ns ns ns ns ns Table 69 provides the SPI input and output AC timing specifications. SPI outputs--Master mode (internal clock) delay SPI outputs--Slave mode (external clock) delay SPI inputs--Master mode (internal clock) input setup time SPI inputs--Master mode (internal clock)input hold time SPI inputs--Slave mode (external clock) input setup time SPI inputs--Slave mode (external clock) input hold time Note: 1 The symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the internal timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X). 2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. The maximum SPICLK input frequency is 66.666 MHz. Figure 48 provides the AC test load for the SPI. Output Z0 = 50 RL = 50 OVDD/2 Figure 48. SPI AC Test Load Figure 49 through Figure 50 represent the AC timing from Table 69. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 75 High-Speed Serial Interfaces (HSSI) Figure 49 shows the SPI timing in slave mode (external clock). SPICLK (input) tNEIVKH tNEIXKH Input Signals: SPIMOSI (See Note) Output Signals: SPIMISO (See Note) tNEKHOV Note: The clock edge is selectable on SPI. Figure 49. SPI AC Timing in Slave Mode (External Clock) Diagram Figure 50 shows the SPI timing in master mode (internal clock). SPICLK (output) tNIIVKH tNIIXKH Input Signals: SPIMISO (See Note) Output Signals: SPIMOSI (See Note) tNIKHOV Note: The clock edge is selectable on SPI. Figure 50. SPI AC Timing in Master Mode (Internal Clock) Diagram 21 High-Speed Serial Interfaces (HSSI) The MPC8377E features two serializer/deserializer (SerDes) interfaces to be used for high-speed serial interconnect applications. See Table 1 for the interfaces supported. This section describes the common portion of SerDes DC electrical specifications, which is the DC requirement for SerDes reference clocks. The SerDes data lane's transmitter and receiver reference circuits are also shown. 21.1 Signal Terms Definition The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms used in the description and specification of differential signals. Figure 51 shows how the signals are defined. For illustration purpose, only one SerDes lane is used for description. The figure shows waveform for either a transmitter output (SDn_TX and SDn_TX) or a receiver input (SDn_RX and SDn_RX). Each signal swings between A volts and B volts where A > B. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 76 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) Using this waveform, the definitions are as follows. To simplify illustration, the following definitions assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling environment. * Single-Ended Swing The transmitter output signals and the receiver input signals SDn_TX, SDn_TX, SDn_RX and SDn_RX each have a peak-to-peak swing of A - B volts. This is also referred as each signal wire's single-ended swing. * Differential Output Voltage, VOD (or Differential Output Swing): The differential output voltage (or swing) of the transmitter, VOD, is defined as the difference of the two complimentary output voltages: VSDn_TX - VSDn_TX. The VOD value can be either positive or negative. * Differential Input Voltage, VID (or Differential Input Swing): The differential input voltage (or swing) of the receiver, VID, is defined as the difference of the two complimentary input voltages: VSDn_RX - VSDn_RX. The VID value can be either positive or negative. * Differential Peak Voltage, VDIFFp The peak value of the differential transmitter output signal or the differential receiver input signal is defined as differential peak voltage, VDIFFp = |A - B| volts. * Differential Peak-to-Peak, VDIFFp-p Since the differential output signal of the transmitter and the differential input signal of the receiver each range from A - B to -(A - B) volts, the peak-to-peak value of the differential transmitter output signal or the differential receiver input signal is defined as differential peak-to-peak voltage, VDIFFp-p = 2 x VDIFFp = 2 x |(A - B)| volts, which is twice of differential swing in amplitude, or twice of the differential peak. For example, the output differential peak-peak voltage can also be calculated as VTX-DIFFp-p = 2 x |VOD|. * Differential Waveform The differential waveform is constructed by subtracting the inverting signal (SDn_TX, for example) from the non-inverting signal (SDn_TX, for example) within a differential pair. There is only one signal trace curve in a differential waveform. The voltage represented in the differential waveform is not referenced to ground. Refer to Figure 60 as an example for differential waveform. * Common Mode Voltage, Vcm The common mode voltage is equal to one half of the sum of the voltages between each conductor of a balanced interchange circuit and ground. In this example, for SerDes output, Vcm_out = (VSDn_TX + VSDn_TX) / 2 = (A + B) / 2, which is the arithmetic mean of the two complimentary output voltages within a differential pair. In a system, the common mode voltage may often differ from one component's output to the other's input. Sometimes it may be even different between the receiver input and driver output circuits within the same component. It is also referred as the DC offset in some occasion. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 77 High-Speed Serial Interfaces (HSSI) A Volts SDn_TX or SDn_RX Vcm = (A + B)/2 SDn_TX or SDn_RX B Volts Differential Swing, VID or VOD = A - B Differential Peak Voltage, VDIFFp = |A - B| Differential Peak-Peak Voltage, VDIFFpp = 2 x VDIFFp (not shown) Figure 51. Differential Voltage Definitions for Transmitter or Receiver To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD or TD) is 500 mVp-p, which is referred as the single-ended swing for each signal. In this example, since the differential signaling environment is fully symmetrical, the transmitter output's differential swing (VOD) has the same amplitude as each signal's single-ended swing. The differential output signal ranges between 500 mV and -500 mV, in other words, VOD is 500 mV in one phase and -500 mV in the other phase. The peak differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p) is 1000 mVp-p. 21.2 SerDes Reference Clocks The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding SerDes lanes. The SerDes reference clocks inputs are SD1_REF_CLK and SD1_REF_CLK for both lanes of SerDes1, and SD2_REF_CLK and SD2_REF_CLK for both lanes of SerDes2. The following sections describe the SerDes reference clock requirements and some application information. 21.2.1 SerDes Reference Clock Receiver Characteristics Figure 52 shows a receiver reference diagram of the SerDes reference clocks. * SerDes Reference Clock Receiver Reference Circuit Structure -- The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as shown in Figure 52. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a 50 termination to SGND_SRDSn (xcorevss) followed by on-chip AC-coupling. -- The external reference clock driver must be able to drive this termination. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 78 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) * * -- The SerDes reference clock input can be either differential or single-ended. Refer to the Differential Mode and Single-ended Mode description below for further detailed requirements. The maximum average current requirement that also determines the common mode voltage range -- When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximum average current of 8 mA (refer to the following bullet for more detail), since the input is AC-coupled on-chip. -- This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V / 50 = 8 mA) while the minimum common mode input level is 0.1 V above SGND_SRDSn (xcorevss). For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0 mA to 16 mA (0-0.8 V), such that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode voltage at 400 mV. -- If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50 to SGND_SRDSn (xcorevss) DC, or it exceeds the maximum input current limitations, then it must be AC-coupled off-chip. The input amplitude requirement -- This requirement is described in detail in the following sections. 50 SDn_REF_CLK Input Amp SDn_REF_CLK 50 Figure 52. Receiver of SerDes Reference Clocks 21.2.2 DC Level Requirement for SerDes Reference Clocks The DC level requirement for the device SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described below. * Differential Mode -- The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-peak (or between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have a single-ended swing less than 800 mV and MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 79 High-Speed Serial Interfaces (HSSI) * greater than 200 mV. This requirement is the same for both external DC-coupled or AC-coupled connection. -- For external DC-coupled connection, as described in Section 21.2.1, "SerDes Reference Clock Receiver Characteristics," the maximum average current requirements sets the requirement for average voltage (common mode voltage) to be between 100 mV and 400 mV. Figure 53 shows the SerDes reference clock input requirement for DC-coupled connection scheme. -- For external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver operate in different command mode voltages. The SerDes reference clock receiver in this connection scheme has its common mode voltage set to SGND_SRDSn. Each signal wire of the differential inputs is allowed to swing below and above the command mode voltage (SGND_SRDSn). Figure 54 shows the SerDes reference clock input requirement for AC-coupled connection scheme. Single-ended Mode -- The reference clock can also be single-ended. The SD _REF_CLK input amplitude (single-ended swing) must be between 400 mV and 800 mVp-p (from Vmin to Vmax) with SDn_REF_CLK either left unconnected or tied to ground. -- The SDn_REF_CLK input average voltage must be between 200 mV and 400 mV. Figure 55 shows the SerDes reference clock input requirement for single-ended signaling mode. -- To meet the input amplitude requirement, the reference clock inputs might need to be DC or AC-coupled externally. For the best noise performance, the reference of the clock could be DC or AC-coupled into the unused phase (SDn_REF_CLK) through the same source impedance as the clock input (SDn_REF_CLK) in use. 200 mV < Input Amplitude or Differential Peak < 800 mV SDn_REF_CLK Vmax < 800 mV 100 mV < V cm < 400 mV SDn_REF_CLK Vmin > 0 V Figure 53. Differential Reference Clock Input DC Requirements (External DC-Coupled) MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 80 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) 200 mV < Input Amplitude or Differential Peak < 800 mV SDn_REF_CLK 150 fdafdV max < Vcm + 400 mV Vmax < Vcm + 400 mV Vcm SDn_REF_CLK Vmin > V cm - 400m V Figure 54. Differential Reference Clock Input DC Requirements (External AC-Coupled) 400 mV < SDn_REF_CLK Input Amplitude < 800 mV SDn_REF_CLK 0V SDn_REF_CLK Figure 55. Single-Ended Reference Clock Input DC Requirements 21.2.3 Interfacing With Other Differential Signaling Levels The following list provides information about interfacing with other differential signaling levels. * With on-chip termination to SGND_SRDSn (xcorevss), the differential reference clocks inputs are HCSL (high-speed current steering logic) compatible DC-coupled. * Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can be used but may need to be AC-coupled due to the limited common mode input range allowed (100 mV to 400 mV) for DC-coupled connection. * LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to AC-coupling. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 81 High-Speed Serial Interfaces (HSSI) NOTE Figure 56 to Figure 59 below are for conceptual reference only. Due to the fact that clock driver chip's internal structure, output impedance, and termination requirements are different between various clock driver chip manufacturers, it is very possible that the clock circuit reference designs provided by the clock driver chip vendor are different from what is shown below. They might also vary from one vendor to the other. Therefore, Freescale Semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits. The system designer is recommended to contact the selected clock driver chip vendor for the optimal reference circuits with the device SerDes reference clock receiver requirement provided in this document. Figure 56 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It assumes that the DC levels of the clock driver chip is compatible with device SerDes reference clock input's DC requirement. HCSL CLK Driver Chip CLK_Out 33 SDn_REF_CLK 50 MPC8377E Clock Driver 33 CLK_Out 100 differential PWB trace SerDes Refer. CLK Receiver SDn_REF_CLK 50 Total 50 . Assume clock driver's output impedance is about 16 . Clock driver vendor dependent source termination resistor Figure 56. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only) Figure 57 shows the SerDes reference clock connection reference circuits for LVDS type clock driver. Since LVDS clock driver's common mode voltage is higher than the device SerDes reference clock input's allowed range (100 to 400 mV), AC-coupled connection scheme must be used. It assumes the LVDS MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 82 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) output driver features a 50- termination resistor. It also assumes that the LVDS transmitter establishes its own common mode level without relying on the receiver or other external component. LVDS CLK Driver Chip CLK_Out 10 nF SDn_REF_CLK 50 MPC8377E Clock Driver 100 differential PWB trace SerDes Refer. CLK Receiver CLK_Out 10 nF SDn_REF_CLK 50 Figure 57. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only) Figure 58 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver. Since LVPECL driver's DC levels (both common mode voltages and output swing) are incompatible with device SerDes reference clock input's DC requirement, AC-coupling has to be used. Figure 58 assumes that the LVPECL clock driver's output impedance is 50 . R1 is used to DC-bias the LVPECL outputs prior to AC-coupling. Its value could be ranged from 140 to 240 depending on clock driver vendor's requirement. R2 is used together with the SerDes reference clock receiver's 50 termination resistor to attenuate the LVPECL output's differential peak level such that it meets the device SerDes reference clock's differential input amplitude requirement (between 200 mV and 800 mV differential peak). For example, if the LVPECL output's differential peak is 900 mV and the desired SerDes reference clock input amplitude is selected as 600 mV, the attenuation factor is 0.67, which requires R2 = 25 . Please consult MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 83 High-Speed Serial Interfaces (HSSI) clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular clock driver chip. LVPECL CLK Driver Chip CLK_Out 10 nF SDn_REF_CLK 50 MPC8377E R2 Clock Driver R1 100 differential PWB trace R2 10 nF SDn_REF_CLK SerDes Refer. CLK Receiver CLK_Out R1 50 Figure 58. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only) Figure 59 shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC levels of the clock driver are compatible with device SerDes reference clock input's DC requirement. Single-Ended CLK Driver Chip Total 50 . Assume clock driver's output impedance is about 16 . 33 CLK_Out SDn_REF_CLK 50 MPC8377E Clock Driver 100 differential PWB trace SerDes Refer. CLK Receiver 50 SDn_REF_CLK 50 Figure 59. Single-Ended Connection (Reference Only) 21.2.4 AC Requirements for SerDes Reference Clocks The clock driver selected should provide a high quality reference clock with low phase noise and cycle-to-cycle jitter. Phase noise less than 100 KHz can be tracked by the PLL and data recovery loops and is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 84 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) occurs in the 1-15 MHz range. The source impedance of the clock driver should be 50 to match the transmission line and reduce reflections which are a source of noise to the system. Table 70 describes some AC parameters common to PCI Express and SATA protocols. Table 70. SerDes Reference Clock Common AC Parameters At recommended operating conditions with XVDD_SRDS or XVDD_SRDS = 1.0 V 5%. Parameter Rising Edge Rate Falling Edge Rate Differential Input High Voltage Differential Input Low Voltage Rising edge rate (SDn_REF_CLK) to falling edge rate (SDn_REF_CLK) matching 1 Symbol Rise Edge Rate Fall Edge Rate VIH VIL Rise-Fall Matching Min 1.0 1.0 200 -- -- Max 4.0 4.0 -- -200 20 Unit V/ns V/ns mV mV % Notes 2, 3 2, 3 2 2 1, 4 Note: Measurement taken from single ended waveform. 2 Measurement taken from differential waveform. 3 Measured from -200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK). The signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered on the differential zero crossing. See Figure 60. 4 Matching applies to rising edge rate for SDn_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a 200 mV window centered on the median cross point where SDn_REF_CLK rising meets SDn_REF_CLK falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of SDn_REF_CLK should be compared to the Fall Edge Rate of SDn_REF_CLK, the maximum allowed difference should not exceed 20% of the slowest edge rate. See Figure 61. Rise Edge Rate Fall Edge Rate VIH = +200 mV 0.0 V VIL = -200 mV SDn_REF_CLK Minus SDn_REF_CLK Figure 60. Differential Measurement Points for Rise and Fall Time TFALL TRISE SDn_REF_CLK SDn_REF_CLK VCROSS MEDIAN +100 mV VCROSS MEDIAN VCROSS MEDIAN VCROSS MEDIAN -100 mV SDn_REF_CLK SDn_REF_CLK Figure 61. Single-Ended Measurement Points for Rise and Fall Time Matching MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 85 Package and Pin Listings 21.3 SerDes Transmitter and Receiver Reference Circuits SD1_TXn or SD2_TXn SD1_RXn or SD2_RXn 50 50 SD1_TXn or SD2_TXn SD1_RXn or SD2_RXn 50 Figure 62 shows the reference circuits for SerDes data lane's transmitter and receiver. 50 Transmitter Receiver Figure 62. SerDes Transmitter and Receiver Reference Circuits The DC and AC specification of SerDes data lanes are defined in each interface protocol section below in this document based on the application usage: * * * Section 8, "Ethernet: Enhanced Three-Speed Ethernet (eTSEC)" Section 15, "PCI Express" Section 16, "Serial ATA (SATA)" Note that an external AC coupling capacitor is required for the above three serial transmission protocols with the capacitor value defined in specification of each protocol section. 22 Package and Pin Listings This section details package parameters, pin assignments, and dimensions. 22.1 Package Parameters for the MPC8377E TePBGA II The package parameters are provided in the following list. The package type is 31 mm x 31 mm, 689 plastic ball grid array (TePBGA II). Package outline 31 mm x 31 mm Interconnects 689 Pitch 1.00 mm Module height (typical) 2.0 mm to 2.46 mm (maximum) Solder Balls 3.5% Ag, 96.5% Sn Ball diameter (typical) 0.60 mm MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 86 Freescale Semiconductor Package and Pin Listings Figure 63 shows the mechanical dimensions and bottom surface nomenclature of the TEPBGA II package. Figure 63. Mechanical Dimensions and Bottom Surface Nomenclature of the TEPBGA II Note: 1 All dimensions are in millimeters. 2 Dimensioning and tolerancing per ASME Y14. 5M-1994. 3 Maximum solder ball diameter measured parallel to Datum A. 4 Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 5 Parallelism measurement should exclude any effect of mark on top surface of package. 22.2 Pinout Listings Table 71. TePBGA II Pinout Listing Signal Package Pin Number Clock Signals CLKIN K24 I OVDD -- Pin Type Power Supply Notes Table 71 provides the pin-out listing for the TePBGA II package. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 87 Package and Pin Listings Table 71. TePBGA II Pinout Listing (continued) Signal PCI_CLK/PCI_SYNC_IN PCI_SYNC_OUT PCI_CLK0 PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4 RTC/PIT_CLOCK Package Pin Number C10 N24 L24 M24 M25 M26 L26 AF11 DDR SDRAM Memory Interface MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 MBA0 MBA1 MBA2 MCAS_B MCK_B0 MCK_B1 MCK_B2 MCK_B3 U3 U1 T5 T3 T2 T1 R1 P2 P1 N4 V3 M5 N1 M2 M1 U5 U4 M3 W5 H1 K1 V1 W2 O O O O O O O O O O O O O O O O O O O O O O O GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pin Type I O O O O O O I Power Supply OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD Notes -- 3 -- -- -- -- -- -- MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 88 Freescale Semiconductor Package and Pin Listings Table 71. TePBGA II Pinout Listing (continued) Signal MCK_B4 MCK_B5 MCK0 MCK1 MCK2 MCK3 MCK4 MCK5 MCKE0 MCKE1 MCS_B0 MCS_B1 MCS_B2 MCS_B3 MDIC0 MDIC1 MDM0 MDM1 MDM2 MDM3 MDM4 MDM5 MDM6 MDM7 MDM8 MDQ0 MDQ1 MDQ2 MDQ3 MDQ4 MDQ5 MDQ6 MDQ7 Package Pin Number AA1 AB2 J1 L1 V2 W1 Y1 AB1 M4 R5 W3 P3 T4 R4 AH8 AJ8 B6 B2 E2 E1 Y6 AC6 AE6 AJ4 L6 A8 A6 C7 D8 A7 A5 A3 C6 Pin Type O O O O O O O O O O O O O O I/O I/O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD Notes -- -- -- -- -- -- -- -- 3 3 -- -- -- -- 9 9 -- -- -- -- -- -- -- -- -- 11 11 11 11 11 11 11 11 MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 89 Package and Pin Listings Table 71. TePBGA II Pinout Listing (continued) Signal MDQ8 MDQ9 MDQ10 MDQ11 MDQ12 MDQ13 MDQ14 MDQ15 MDQ16 MDQ17 MDQ18 MDQ19 MDQ20 MDQ21 MDQ22 MDQ23 MDQ24 MDQ25 MDQ26 MDQ27 MDQ28 MDQ29 MDQ30 MDQ31 MDQ32 MDQ33 MDQ34 MDQ35 MDQ36 MDQ37 MDQ38 MDQ39 MDQ40 Package Pin Number D7 E8 B1 D5 B3 D6 C3 C2 D4 E6 F6 G4 F8 E4 C1 G6 F2 G5 H6 H4 D1 G3 H5 F1 W6 AC1 AC3 AE1 V6 Y5 AA4 AB6 AD3 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD Notes 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 90 Freescale Semiconductor Package and Pin Listings Table 71. TePBGA II Pinout Listing (continued) Signal MDQ41 MDQ42 MDQ43 MDQ44 MDQ45 MDQ46 MDQ47 MDQ48 MDQ49 MDQ50 MDQ51 MDQ52 MDQ53 MDQ54 MDQ55 MDQ56 MDQ57 MDQ58 MDQ59 MDQ60 MDQ61 MDQ62 MDQ63 MDQS0 MDQS1 MDQS2 MDQS3 MDQS4 MDQS5 MDQS6 MDQS7 MDQS8 MECC0/MSRCID0 Package Pin Number AC4 AD4 AF1 AE4 AC5 AE2 AE3 AG1 AG2 AG3 AF5 AE5 AD7 AH2 AG4 AH3 AG5 AF8 AJ5 AF6 AF7 AH6 AH7 C8 C4 E3 G2 AB5 AD1 AH1 AJ3 G1 J6 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD Notes 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 -- MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 91 Package and Pin Listings Table 71. TePBGA II Pinout Listing (continued) Signal MECC1/MSRCID1 MECC2/MSRCID2 MECC3/MSRCID3 MECC4/MSRCID4 MECC5/MDVAL MECC6 MECC7 MODT0 MODT1 MODT2 MODT3 MRAS_B MVREF1 MVREF2 MWE_B Package Pin Number J3 K2 K3 J5 J2 L5 L2 N5 U6 M6 P6 AA3 K4 W4 Y2 DUART Interface UART_SIN1/MSRCID2/LSRCID2 UART_SOUT1/MSRCID0/LSRCID0 UART_CTS_B[1]/MSRCID4/LSRCID4 UART_RTS_B1 UART_SIN2/MSRCID3/ LSRCID3 UART_SOUT2/MSRCID1/LSRCID1 UART_CTS_B[2]/MDVAL/LDVAL UART_RTS_B[2] L28 L27 K26 N27 K27 K28 K29 L29 Enhanced Local Bus Controller (eLBC) Interface LAD0 LAD1 LAD2 LAD3 LAD4 LAD5 LAD6 E24 G28 H25 F26 C26 J28 F21 I/O I/O I/O I/O I/O I/O I/O LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD -- -- -- -- -- -- -- I/O O I/O O I/O O I/O O OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD -- -- -- -- -- -- -- -- Pin Type I/O I/O I/O I/O I/O I/O I/O O O O O O I I O Power Supply GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD Notes -- -- -- -- -- -- -- 6 6 6 6 -- 11 11 -- MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 92 Freescale Semiconductor Package and Pin Listings Table 71. TePBGA II Pinout Listing (continued) Signal LAD7 LAD8 LAD9 LAD10 LAD11 LAD12 LAD13 LAD14 LAD15 LA11/LAD16 LA12/LAD17 LA13/LAD18 LA14/LAD19 LA15/LAD20 LA16/LAD21 LA17/LAD22 LA18/LAD23 LA19/LAD24 LA20/LAD25 LA21/LAD26 LA22/LAD27 LA23/LAD28 LA24/LAD29 LA25/LAD30 LA26/LAD31 LA27 LA28 LA29 LA30 LA31 LA10/LALE LBCTL LCLK0 Package Pin Number F23 E25 E26 A23 F24 G24 F25 H28 G25 F27 B21 A25 C28 H24 E23 B28 D28 A27 C25 B27 H27 E21 F20 D29 E20 H26 C29 E28 B26 J25 H29 A22 B22 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O Power Supply LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD Notes -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 93 Package and Pin Listings Table 71. TePBGA II Pinout Listing (continued) Signal LCLK1 LCLK2 LCS_B0 LCS_B1 LCS_B2 LCS_B3 LCS_B4/LDP0 LCS_B5/LDP1 LA7/LCS_B6/LDP2 LA8/LCS_B7/LDP3 LFCLE/LGPL0 LFALE/LGPL1 LFRE_B/LGPL2/LOE_B LFWP_B/LGPL3 LGPL4/LFRB_B/LGTA_B/ LUPWAIT/LPBSE LA9/LGPL5 LSYNC_IN LSYNC_OUT LWE_B0/LFWE0/LBS_B0 LWE_B1/LFWE1/LBS_B1 LWE_B2/LFWE2/LBS_B2 LWE_B3/LFWE3/LBS_B3 Package Pin Number C23 B23 D25 F19 C27 D24 C24 B29 E29 F29 D21 A26 F22 C21 J29 G29 A21 D23 E22 B25 E27 F28 eTSEC1/GPIO1/GPIO2/CFG_RESET Interface TSEC1_COL/GPIO2[20] TSEC1_CRS/GPIO2[21] TSEC1_GTX_CLK TSEC1_RX_CLK TSEC1_RX_DV TSEC1_RX_ER/GPIO2[25] TSEC1_RXD0 TSEC1_RXD1 TSEC1_RXD2 AF22 AE20 AJ25 AG22 AD19 AD20 AD22 AE21 AE22 I/O I/O O I I I/O I I I LVDD1 LVDD1 LVDD1 LVDD1 LVDD1 LVDD1 LVDD1 LVDD1 LVDD1 -- -- -- -- -- -- -- -- -- Pin Type O O O O O O I/O I/O I/O I/O O O O O I/O O I O O O O O Power Supply LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD LBVDD Notes -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 94 Freescale Semiconductor Package and Pin Listings Table 71. TePBGA II Pinout Listing (continued) Signal TSEC1_RXD3 TSEC1_TX_CLK TSEC1_TX_EN TSEC1_TX_ER/CFG_LBMUX TSEC1_TXD0/ CFG_RESET_SOURCE[0] TSEC1_TXD1/ CFG_RESET_SOURCE[1] TSEC1_TXD2/ CFG_RESET_SOURCE[2] TSEC1_TXD3/ CFG_RESET_SOURCE[3] EC_GTX_CLK125 EC_MDC/CFG_CLKIN_DIV EC_MDIO Package Pin Number AD21 AJ22 AG23 AH22 AD23 AE23 AF23 AJ24 AH24 AJ21 AH21 eTSEC2/GPIO1 Interface TSEC2_COL/GPIO1[21]/ TSEC1_TMR_TRIG1 TSEC2_CRS/GPIO1[22]/ TSEC1_TMR_TRIG2 TSEC2_GTX_CLK TSEC2_RX_CLK/ TSEC1_TMR_CLK TSEC2_RX_DV/GPIO1[23] TSEC2_RX_ER/GPIO1[25] TSEC2_RXD0/GPIO1[16] TSEC2_RXD1/GPIO1[15] TSEC2_RXD2/GPIO1[14] TSEC2_RXD3/GPIO1[13] TSEC2_TX_CLK/GPIO2[24]/ TSEC1_TMR_GCLK TSEC2_TX_EN/GPIO1[12]/ TSEC1_TMR_ALARM2 TSEC2_TX_ER/GPIO1[24]/ TSEC1_TMR_ALARM1 TSEC2_TXD0/GPIO1[20] AJ27 AG29 AF28 AF25 AF26 AG25 AE28 AE29 AH26 AH25 AG28 AJ26 AG26 AH28 I/O I/O O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O LVDD2 LVDD2 LVDD2 LVDD2 LVDD2 LVDD2 LVDD2 LVDD2 LVDD2 LVDD2 LVDD2 LVDD2 LVDD2 LVDD2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pin Type I I O I/O I/O I/O I/O I/O I I/O I/O Power Supply LVDD1 LVDD1 LVDD1 LVDD1 LVDD1 LVDD1 LVDD1 LVDD1 LVDD1 LVDD1 LVDD1 Notes -- -- -- -- -- -- -- -- -- -- -- MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 95 Package and Pin Listings Table 71. TePBGA II Pinout Listing (continued) Signal TSEC2_TXD1/GPIO1[19]/ TSEC1_TMR_PP1 TSEC2_TXD2/GPIO1[18]/ TSEC1_TMR_PP2 TSEC2_TXD3/GPIO1[17]/ TSEC1_TMR_PP3 Package Pin Number AF27 AJ28 AF29 Pin Type I/O I/O I/O Power Supply LVDD2 LVDD2 LVDD2 Notes -- -- -- GPIO1 Interface GPIO1[0]/GTM1_TIN1/ GTM2_TIN2/DREQ0_B GPIO1[1]/GTM1_TGATE1_B/ GTM2_TGATE2_B/DACK0_B GPIO1[2]/GTM1_TOUT1_B/ DDONE0_B GPIO1[3]/GTM1_TIN2/ GTM2_TIN1/DREQ1_B GPIO1[4]/GTM1_TGATE2_B/ GTM2_TGATE1_B/DACK1_B GPIO1[5]/GTM1_TOUT2_B/ GTM2_TOUT1_B/DDONE1_B GPIO1[6]/GTM1_TIN3/ GTM2_TIN4/DREQ2_B GPIO1[7]/GTM1_TGATE3_B/ GTM2_TGATE4_B/DACK2_B GPIO1[8]/GTM1_TOUT3_B/ DDONE2_B GPIO1[9]/GTM1_TIN4/ GTM2_TIN3/DREQ3_B GPIO1[10]/GTM1_TGATE4_B/GTM2_T GATE3_B/DACK3_B GPIO1[11]/GTM1_TOUT4_B/ GTM2_TOUT3_B/DDONE3_B P25 N25 N26 B9 N29 M29 A9 B10 J26 J24 J27 P24 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD -- -- -- -- -- -- -- -- -- -- -- -- USB/GPIO2 Interface USBDR_CLK/GPIO2[23] USBDR_DIR_DPPULLUP/GPIO2[9] USBDR_NXT/GPIO2[8] USBDR_PCTL0/GPIO2[11]/SD_DAT2 USBDR_PCTL1/GPIO2[22]/SD_DAT3 AJ11 AG12 AJ10 AF10 AE9 I/O I/O I/O I/O I/O OVDD OVDD OVDD OVDD OVDD -- -- -- -- -- MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 96 Freescale Semiconductor Package and Pin Listings Table 71. TePBGA II Pinout Listing (continued) Signal USBDR_PWRFAULT/ GPIO2[10]/SD_DAT1 USBDR_STP_SUSPEND USBDR_D0_ENABLEN/GPIO2[0] USBDR_D1_SER_TXD/GPIO2[1] USBDR_D2_VMO_SE0/GPIO2[2] USBDR_D3_SPEED/GPIO2[3] USBDR_D4_DP/GPIO2[4] USBDR_D5_DM/GPIO2[5] USBDR_D6_SER_RCV/GPIO2[6] USBDR_D7_DRVVBUS/GPIO2[7] Package Pin Number AG13 AH12 AG10 AF13 AG11 AH11 AG9 AF9 AH13 AH10 I2C Interface IIC1_SCL IIC1_SDA IIC2_SCL IIC2_SDA C12 B12 A10 A12 JTAG Interface TCK TDI TDO TMS TRST_B B13 E14 C13 A13 E11 PCI Signals PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 P26 N28 P29 P27 R26 R29 T24 T25 R27 I/O I/O I/O I/O I/O I/O I/O I/O I/O OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD -- -- -- -- -- -- -- -- -- I I O I I OVDD OVDD OVDD OVDD OVDD -- 4 3 4 4 I/O I/O I/O I/O OVDD OVDD OVDD OVDD 2 2 2 2 Pin Type I/O O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD Notes -- 12 -- -- -- -- -- -- -- -- MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 97 Package and Pin Listings Table 71. TePBGA II Pinout Listing (continued) Signal PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_C_BE_B0 PCI_C_BE_B1 PCI_C_BE_B2 PCI_C_BE_B3 PCI_DEVSEL_B PCI_FRAME_B PCI_GNT_B0 PCI_GNT_B[1]/CPCI_HS_LED PCI_GNT_B[2]/CPCI_HS_ENUM PCI_GNT_B[3]/PCI_PME Package Pin Number P28 U25 R28 U26 U24 T29 V24 Y26 V28 AA25 AA26 W29 AA24 AA27 AC26 AB25 AB24 AA28 AA29 AC24 AC25 AB28 AE24 T26 T28 V29 Y29 U28 V27 AE27 AC28 AD27 AC27 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O Power Supply OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD Notes -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 5 -- -- -- -- -- MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 98 Freescale Semiconductor Package and Pin Listings Table 71. TePBGA II Pinout Listing (continued) Signal PCI_GNT_B[4] PCI_IDSEL PCI_INTA_B/IRQ_OUT_B PCI_IRDY_B PCI_PAR PCI_PERR_B PCI_REQ_B0 PCI_REQ_B[1]/CPCI_HS_ES PCI_REQ_B2 PCI_REQ_B3 PCI_REQ_B4 PCI_RESET_OUT_B PCI_SERR_B PCI_STOP_B PCI_TRDY_B M66EN Package Pin Number AE25 W28 AD29 U29 V25 Y25 AE26 AC29 AB29 AD26 W27 AD28 V26 W26 Y24 AD15 Programmable Interrupt Controller (PIC) Interface MCP_OUT_B IRQ_B0/MCP_IN_B/GPIO2[12] IRQ_B1/GPIO2[13] IRQ_B2/GPIO2[14] IRQ_B3/GPIO2[15] IRQ_B4/GPIO2[16] IRQ_B5/GPIO2[17]/ USBDR_PWRFAULT IRQ_B6/GPIO2[18] IRQ_B7/GPIO2[19] AD14 F9 E9 F10 D9 C9 AE10 AD10 AD9 PMC Interface QUIESCE_B D13 SerDes1 Interface L1_SD_IMP_CAL_RX L1_SD_IMP_CAL_TX AJ14 AG19 I I L1_XPADVDD L1_XPADVDD -- -- O OVDD -- O I/O I/O I/O I/O I/O I/O I/O I/O OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD 2 -- -- -- -- -- -- -- -- Pin Type O I O I/O I/O I/O I/O I I I I O I/O I/O I/O I Power Supply OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD Notes -- 5 2 5 -- 5 -- -- -- -- -- -- 5 5 5 -- MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 99 Package and Pin Listings Table 71. TePBGA II Pinout Listing (continued) Signal L1_SD_REF_CLK L1_SD_REF_CLK_B L1_SD_RXA_N L1_SD_RXA_P L1_SD_RXE_N L1_SD_RXE_P L1_SD_TXA_N L1_SD_TXA_P L1_SD_TXE_N L1_SD_TXE_P L1_SDAVDD_0 Package Pin Number AJ17 AH17 AJ15 AH15 AJ19 AH19 AF15 AE15 AF18 AE18 AJ18 Pin Type I I I I I I O O O O SerDes PLL Power (1.0 or 1.05 V) SerDes PLL GND SerDes Core Power (1.0 or 1.05 V) SerDes Core GND SerDes I/O Power (1.0 or 1.05 V) SerDes I/O GND Power Supply L1_XPADVDD L1_XPADVDD L1_XPADVDD L1_XPADVDD L1_XPADVDD L1_XPADVDD L1_XPADVDD L1_XPADVDD L1_XPADVDD L1_XPADVDD -- Notes -- -- -- -- -- -- -- -- -- -- -- L1_SDAVSS_0 L1_XCOREVDD AG17 AH14, AJ16, AF17, AH20, AJ20 -- -- -- -- L1_XCOREVSS L1_XPADVDD AG14, AG15, AG16, AH16, AG18, AG20 AE16, AF16, AD18, AE19, AF19 -- -- -- -- L1_XPADVSS AF14, AE17, AF20 -- -- SerDes2 Interface L2_SD_IMP_CAL_RX L2_SD_IMP_CAL_TX L2_SD_REF_CLK L2_SD_REF_CLK_B L2_SD_RXA_N L2_SD_RXA_P L2_SD_RXE_N L2_SD_RXE_P L2_SD_TXA_N C19 C15 B17 A17 A19 B19 A15 B15 D18 I I I I I I I I O L2_XPADVDD L2_XPADVDD L2_XPADVDD L2_XPADVDD L2_XPADVDD L2_XPADVDD L2_XPADVDD L2_XPADVDD L2_XPADVDD -- -- -- -- -- -- -- -- -- MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 100 Freescale Semiconductor Package and Pin Listings Table 71. TePBGA II Pinout Listing (continued) Signal L2_SD_TXA_P L2_SD_TXE_N L2_SD_TXE_P L2_SDAVDD_0 Package Pin Number E18 D15 E15 A16 Pin Type O O O SerDes PLL Power (1.0 or 1.05 V) SerDes PLL GND SerDes Core Power (1.0 or 1.05 V) SerDes Core GND SerDes I/O Power (1.0 or 1.05 V) SerDes I/O GND Power Supply L2_XPADVDD L2_XPADVDD L2_XPADVDD -- Notes -- -- -- -- L2_SDAVSS_0 L2_XCOREVDD C17 A14, B14, D17, B18, B20 -- -- -- -- L2_XCOREVSS L2_XPADVDD C14, C16, A18, C18, A20, C20 D14, E16, F18, D19, E19 -- -- -- -- L2_XPADVSS D16, E17, D20 -- -- SPI Interface SPICLK/SD_CLK SPIMISO/SD_DAT0 SPIMOSI/SD_CMD SPISEL_B/SD_CD AH9 AD11 AJ9 AE11 System Control Interface SRESET_B HRESET_B PORESET_B AD12 AE12 AE14 Test Interface TEST E10 Thermal Management Reserved F15 Power Supply Signals I -- 13 I OVDD 10 I/O I/O I OVDD OVDD OVDD 2 1 -- I/O I/O I/O I OVDD OVDD OVDD OVDD -- -- -- -- MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 101 Package and Pin Listings Table 71. TePBGA II Pinout Listing (continued) Signal LVDD1 Package Pin Number AC21, AG21, AH23 Pin Type Power for eTSEC 1 I/O (2.5 V, 3.3 V) Power for eTSEC 2 I/O (2.5 V, 3.3 V) Power for eLBC (3.3, 2.5, or 1.8 V) Power for Core (1.0 V or 1.5 V) Power Supply LVDD1 Notes -- LVDD2 AG24, AH27, AH29 LVDD2 -- LBVDD G20, D22, A24, G26, D27, A28 LBVDD -- VDD K10, L10, M10, N10, P10, R10, T10, U10, V10, W10, Y10, K11, R11, Y11, K12, Y12, K13, Y13, K14, Y14, K15, L15, W15, Y15, K16, Y16, K17, Y17, K18, Y18, K19, R19, Y19, K20, L20, M20, N20, P20, R20, T20, U20, V20, W20, Y20 A1, AJ1, H2, N2, AA2, AD2, D3, R3, AF3, A4, F4, J4, L4, V4, Y4, AB4, B5, E5, P5, AH5, K6, T6, AA6, AD6, AG6, F7, J7, Y7, AJ7, B8, AE8, AG8, G9, AC9, B11, D11, F11, L11, M11, N11, P11, T11, U11, V11, W11, L12, M12, N12, P12, R12, T12, U12, V12, W12, E12, E13, L13, M13, N13, P13, R13, T13, U13, V13, W13, AE13, AJ13, F14, L14, M14, N14, P14, R14, T14, U14, V14, W14, M15, N15, P15, R15, T15, U15, V15, L16, M16, N16, P16, R16, T16, U16, V16, W16, L17, M17, N17, P17, R17, T17, U17, V17, W17, L18, M18, N18, P18, R18, T18, U18, V18, W18, L19, M19, N19, P19, T19, U19, V19, W19, AC20, G21, AF21, C22, J23, AA23, AJ23, B24, W24, AF24, K25, R25, AD25, D26, G27, M27, T27, Y27, AB27, AG27, A29, AJ29 AD13 VDD -- GND (VSS) -- -- -- AVDD_C Power for e300 PLL (1.0 or 1.05 V) Power for eLBC PLL (1.0 or 1.05 V) Power for system PLL (1.0 V) -- -- AVDD_L F13 -- -- AVDD_P F12 -- -- MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 102 Freescale Semiconductor Package and Pin Listings Table 71. TePBGA II Pinout Listing (continued) Signal GVDD Package Pin Number A2, D2, R2, U2, AC2, AF2, AJ2, F3, H3, L3, N3, Y3, AB3, B4, P4, AF4, AH4, C5, F5, K5, V5, AA5, AD5, N6, R6, AJ6, B7, E7, K7, AA7, AE7, AG7, AD8 AC10, D10, D12, AF12, AJ12, K23, Y23, R24, AD24, L25, W25, AB26, U27, M28, Y28, G10, A11, C11 Pin Type Power for DDR SDRAM I/O Voltage (2.5 or 1.8 V) PCI, USB, and other Standard (3.3 V) Power Supply GVDD Notes -- OVDD OVDD -- No Connect NC F16, F17, AD16, AD17 Pull Down Pull Down B16, AH18 -- -- 7 -- -- 8 Note: 1 This pin is an open drain signal. A weak pull-up resistor (1 k) should be placed on this pin to OVDD. 2 This pin is an open drain signal. A weak pull-up resistor (2-10 k) should be placed on this pin to OVDD. 3 This output is actively driven during reset rather than being released to high impedance during reset. 4 These JTAG pins have weak internal pull-up P-FETs that are always enabled. 5 This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI Specification recommendation and see AN3665, MPC837xE Design Checklist, for more details. 6 These are On Die Termination pins, used to control DDR2 memories internal termination resistance. 7 This pin must always be tied to GND using a 0 resistor. 8 This pin must always be left not connected. 9 For DDR2 operation, it is recommended that MDIC0 be tied to GND using an 18.2 resistor and MDIC1 be tied to DDR power using an 18.2 resistor. 10 This pin must always be tied low. If it is left floating it may cause the device to malfunction. 11 See AN3665, "MPC837xE Design Checklist," for proper DDR termination. 12 This pin must not be pulled down during PORESET. 13 Open or tie to GND. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 103 Clocking 23 Clocking Figure 64 shows the internal distribution of clocks within the MPC8377E. e300 core Core PLL core_clk csb_clk to DDR memory controller ddr_clk System PLL Clock Unit lbiu_clk DDR Clock Div /2 6 6 MCK[0:5] MCK[0:5] DDR Memory Device /n to local bus memory LBIU controller DLL LCLK[0:2] LSYNC_OUT LSYNC_IN PCI_CLK/ PCI_SYNC_IN Local Bus Memory Device csb_clk to rest of the device CFG_CLKIN_DIV CLKIN PCI Clock Divider 5 PCI_SYNC_OUT PCI_CLK[0:4] Figure 64. MPC8377E Clock Subsystem The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. When the device is configured as a PCI host device, CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (/2) and the multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICOEn] parameters select whether CFG_CLKIN_DIV is driven out on the PCI_CLK_OUTn signals. PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN, with equal delay to all PCI agent devices in the system, to allow the device to function. When the device is configured as a PCI agent device, PCI_CLK is the primary input clock. When the device is configured as a PCI agent device the CLKIN signal should be tied to GND. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 104 Freescale Semiconductor Clocking As shown in Figure 64, the primary clock input (frequency) is multiplied up by the system phase-locked loop (PLL) and the clock unit to create the coherent system bus clock (csb_clk), the internal clock for the DDR controller (ddr_clk), and the internal clock for the local bus interface unit (lbiu_clk). The csb_clk frequency is derived from a complex set of factors that can be simplified into the following equation: csb_clk = {PCI_SYNC_IN x (1 + CFG_CLKIN_DIV)} x SPMF In PCI host mode, PCI_SYNC_IN x (1 + CFG_CLKIN_DIV) is the CLKIN frequency. The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies up the csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL) which is loaded at power-on reset or by one of the hard-coded reset options. See Chapter 4, "Reset, Clocking, and Initialization," in the MPC8379E Reference Manual for more information on the clock subsystem. The internal ddr_clk frequency is determined by the following equation: ddr_clk = csb_clk x (1 + RCWL[DDRCM]) Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider (/2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate is the same frequency as ddr_clk. The internal lbiu_clk frequency is determined by the following equation: lbiu_clk = csb_clk x (1 + RCWL[LBCM]) Note that lbiu_clk is not the external local bus frequency; lbiu_clk passes through the LBIU clock divider to create the external local bus clock outputs (LCLK[0:2]). The eLBC clock divider ratio is controlled by LCCR[CLKDIV]. Some of the internal units may be required to be shut off or operate at lower frequency than the csb_clk frequency. Those units have a default clock ratio that can be configured by a memory mapped register after the device comes out of reset. Table 72 specifies which units have a configurable clock frequency. Table 72. Configurable Clock Units Unit eTSEC1, eTSEC2 eSDHC and I2C1 1 Default Frequency csb_clk/3 csb_clk/3 csb_clk/3 csb_clk/3 csb_clk csb_clk/3 csb_clk/3 2 2 Options Off, csb_clk, csb_clk/2, csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 Off, csb_clk Off, csb_clk, csb_clk/2, csb_clk/3 Off, csb_clk Security block USB DR PCI and DMA complex PCI Express1, 2 SATA1, 2 1 This only applies to I C1 (I C2 clock is not configurable). MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 105 Clocking Table 73 provides the operating frequencies for the TePBGA II package under recommended operating conditions (see Table 3). Table 73. Operating Frequencies for TePBGA II Parameter 1 e300 core frequency (core_clk) Coherent system bus frequency (csb_clk) DDR2 memory bus frequency (MCK) 2 DDR1 memory bus frequency (MCK) Local bus frequency (LCLKn) 3 Local bus controller frequency (lbc_clk) PCI input frequency (CLKIN or PCI_CLK) eTSEC frequency Security encryption controller frequency USB controller frequency eSDHC controller frequency PCI Express controller frequency SATA controller frequency Note: The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk, MCK, LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value of SCCR[xCM] must be programmed such that the maximum internal operating frequency of the Security core, USB modules, SATA, and eSDHC will not exceed their respective value listed in this table. 2 The DDR data rate is 2x the DDR memory bus frequency. 3 The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x the csb_clk frequency (depending on RCWL[LBIUCM]). 1 2 Minimum Operating Frequency (MHz) 333 133 125 167 -- -- 25 -- -- -- -- -- -- Maximum Operating Frequency (MHz) 800 400 200 333 133 400 66 400 200 200 200 400 200 23.1 System PLL Configuration The system PLL is controlled by the RCWL[SPMF] parameter. The system PLL VCO frequency depends on RCWL[DDRCM] and RCWL[LBCM]. Table 74 shows the multiplication factor encodings for the system PLL. NOTE If RCWL[DDRCM] and RCWL[LBCM] are both cleared, the system PLL VCO frequency = (CSB frequency) x (System PLL VCO Divider). If either RCWL[DDRCM] or RCWL[LBCM] are set, the system PLL VCO frequency = 2 x (CSB frequency) x (System PLL VCO Divider). The VCO divider needs to be set properly so that the System PLL VCO frequency is in the range of 400-800 MHz. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 106 Freescale Semiconductor Clocking Table 74. System PLL Multiplication Factors RCWL[SPMF] 0000 0001 0010 0011 0100 0101 0110 0111-1111 System PLL Multiplication Factor Reserved Reserved x2 x3 x4 x5 x6 x 7 to x 15 As described in Section 23, "Clocking," The LBIUCM, DDRCM, and SPMF parameters in the reset configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 76 and Table 77 show the expected frequency values for the CSB frequency for select csb_clk to CLKIN/PCI_SYNC_IN ratios. The RCWL[SVCOD] denotes the system PLL VCO internal frequency as shown in Table 75. Table 75. System PLL VCO Divider RCWL[SVCOD] 00 01 10 11 VCO Division Factor 4 8 2 1 Table 76. CSB Frequency Options for Host Mode Input Clock Frequency (MHz) 2 CFG_CLKIN_DIV at Reset 1 SPMF csb_clk : Input Clock Ratio 2 25 csb_clk 33.33 Frequency (MHz) 66.67 -- 133 High High High High 0010 0011 0100 0101 2:1 3:1 4:1 5:1 100 125 100 133 167 -- -- -- MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 107 Clocking Table 76. CSB Frequency Options for Host Mode (continued) Input Clock Frequency (MHz) 2 CFG_CLKIN_DIV at Reset 1 SPMF csb_clk : Input Clock Ratio 2 25 csb_clk 33.33 Frequency (MHz) -- 66.67 -- High High High High High High High High High High 1 2 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 6:1 7:1 8:1 9:1 10 : 1 11 : 1 12 : 1 13 : 1 14 : 1 15 : 1 CFG_CLKIN_DIV select the ratio between CLKIN and PCI_SYNC_OUT. CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode. Table 77. CSB Frequency Options for Agent Mode Input Clock Frequency (MHz) 2 25 csb_clk Low Low Low Low 0010 0011 0100 0101 2:1 3:1 4:1 5:1 -- 125 100 133 -- 33.33 Frequency (MHz) 66.67 -- 133 -- -- -- CFG_CLKIN_DIV at reset 1 SPMF csb_clk : Input Clock Ratio 2 MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 108 Freescale Semiconductor Clocking Table 77. CSB Frequency Options for Agent Mode (continued) Input Clock Frequency (MHz) 2 25 csb_clk Low Low Low Low Low Low Low Low Low Low 1 2 CFG_CLKIN_DIV at reset 1 SPMF csb_clk : Input Clock Ratio 2 33.33 Frequency (MHz) 200 233 266 300 333 66.67 -- 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 6:1 7:1 8:1 9:1 10 : 1 11 : 1 12 : 1 13 : 1 14 : 1 15 : 1 150 175 200 225 250 275 300 325 CFG_CLKIN_DIV doubles csb_clk if set high. CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode. 23.2 Core PLL Configuration RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300 core clock (core_clk). Table 78 shows the encodings for RCWL[COREPLL]. COREPLL values that are not listed in Table 78 should be considered as reserved. NOTE Core VCO frequency = core frequency x VCO divider VCO divider has to be set properly so that the core VCO frequency is in the range of 800-1600 MHz. Table 78. e300 Core PLL Configuration RCWL[COREPLL] VCO Divider 1 core_clk : csb_clk Ratio 0-1 nn 2-5 0000 6 0 PLL bypassed (PLL off, csb_clk clocks core directly) n/a 1:1 1:1 1:1 PLL bypassed (PLL off, csb_clk clocks core directly) n/a 2 4 8 11 00 01 10 nnnn 0001 0001 0001 n 0 0 0 MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 109 Clocking Table 78. e300 Core PLL Configuration (continued) RCWL[COREPLL] VCO Divider 1 core_clk : csb_clk Ratio 0-1 00 01 10 00 01 10 00 01 10 00 01 10 00 01 10 00 01 10 1 2-5 0001 0001 0001 0010 0010 0010 0010 0010 0010 0011 0011 0011 0011 0011 0011 0100 0100 0100 6 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1.5:1 1.5:1 1.5:1 2:1 2:1 2:1 2.5:1 2.5:1 2.5:1 3:1 3:1 3:1 3.5:1 3.5:1 3.5:1 4:1 4:1 4:1 2 4 8 2 4 8 2 4 8 2 4 8 2 4 8 2 4 8 Note: Core VCO frequency = Core frequency x VCO divider. Note that VCO divider has to be set properly so that the core VCO frequency is in the range of 800-1600 MHz. 23.3 Suggested PLL Configurations Table 79. Example Clock Frequency Combinations eLBC 1 e300 Core 1 /8 15.6 18.8 20.8 16.7 x1 -- -- -- -- x 1.5 -- -- -- -- x2 -- -- 333 -- x 2.5 -- 375 416 333 x3 375 450 500 400 Table 79 shows suggested PLL configurations for different input clocks (LBCM = 0). Ref 1 LBCM DDRCM SVCOD SPMF 25.0 25.0 33.3 33.3 0 0 0 0 1 1 1 1 2 2 2 2 5 6 5 4 DDR data Sys CSB1,3 rate1,4 VCO1,2 500 600 667 533 125 150 167 133 250 300 333 267 /2 62.5 75 6 83.3 6 /4 31.3 37.5 41.6 33.3 66.7 MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 110 Freescale Semiconductor Thermal Table 79. Example Clock Frequency Combinations (continued) eLBC 1 Ref 1 LBCM DDRCM SVCOD SPMF 48.0 66.7 25.0 33.3 50.0 50.0 66.7 66.7 66.7 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 2 2 4 2 4 2 2 2 2 3 2 8 8 4 8 4 5 6 DDR data Sys CSB1,3 rate1,4 VCO1,2 576 533 800 533 800 800 533 667 800 144 133 200 266.7 200 400 266.7 333 400 288 266 200 267 200 400 5 e300 Core 1 /8 18 16.7 25 33.3 25 x1 -- -- -- -- -- -- -- 333 400 x 1.5 -- -- -- 400 -- 600 400 500 600 x2 -- -- 400 533 400 800 533 667 800 x 2.5 360 333 500 667 500 -- 667 -- -- x3 432 400 600 800 600 -- 800 -- -- /2 72 6 66.7 100 6 /4 36 33.3 50 66.7 50 100 6 133 6 100 -- 133 6 -- -- 6 50 33.3 267 333 400 5 66.7 83.3 6 41.6 100 6 50 Note: 1 Values in MHz. 2 System PLL VCO range: 400-800 MHz. 3 CSB frequencies less than 133 MHz will not support Gigabit Ethernet rates. 4 Minimum data rate for DDR2 is 250 MHz and for DDR1 is 167 MHz. 5 Applies to DDR2 only. 6 Applies to eLBC PLL-enabled mode only. 24 Thermal This section describes the thermal specifications of the MPC8377E. 24.1 Thermal Characteristics Table 80. Package Thermal Characteristics for TePBGA II Parameter Symbol RJA RJA RJMA RJMA RJB RJC Value 21 15 16 12 8 6 Unit C/W C/W C/W C/W C/W C/W Notes 1, 2 1, 2, 3 1, 3 1, 3 4 5 Table 80 provides the package thermal characteristics for the 689 31 x 31mm TePBGA II package. Junction-to-ambient natural convection on single layer board (1s) Junction-to-ambient natural convection on four layer board (2s2p) Junction-to-ambient (at 200 ft/min) on single layer board (1s) Junction-to-ambient (at 200 ft/min) on four layer board (2s2p) Junction-to-board thermal Junction-to-case thermal MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 111 Thermal Table 80. Package Thermal Characteristics for TePBGA II (continued) Parameter Junction-to-package natural convection on top Symbol JT Value 6 Unit C/W Notes 6 Note: 1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. 3 Per JEDEC JESD51-6 with the board horizontal. 4 Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 24.2 Thermal Management Information For the following sections, PD = (VDD x IDD) + PI/O where PI/O is the power dissipation of the I/O drivers. 24.2.1 Estimation of Junction Temperature with Junction-to-Ambient Thermal Resistance TJ = TA + (RJA x PD) where: TJ = junction temperature (C) TA = ambient temperature for the package (C) RJA = junction to ambient thermal resistance (C/W) PD = power dissipation in the package (W) An estimation of the chip junction temperature, TJ, can be obtained from the equation: The junction to ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance. Generally, the value obtained on a single layer board is appropriate for a tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. Test cases have demonstrated that errors of a factor of two (in the quantity TJ - TA) are possible. 24.2.2 Estimation of Junction Temperature with Junction-to-Board Thermal Resistance NOTE The heat sink cannot be mounted on the package. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 112 Freescale Semiconductor Thermal The thermal performance of a device cannot be adequately predicted from the junction to ambient thermal resistance. The thermal performance of any component is strongly dependent on the power dissipation of surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: TJ = TA + (RJB x PD) where: TA = ambient temperature for the package (C) RJB = junction to board thermal resistance (C/W) per JESD51-8 PD = power dissipation in the package (W) When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition: the component is soldered to a board with internal planes. 24.2.3 Experimental Determination of Junction Temperature NOTE The heat sink cannot be mounted on the package. To determine the junction temperature of the device in the application after prototypes are available, use the thermal characterization parameter (JT) to determine the junction temperature and a measure of the temperature at the top center of the package case using the following equation: TJ = TT + (JT x PD) where: TJ = junction temperature (C) TT = thermocouple temperature on top of package (C) JT = junction to ambient thermal resistance (C/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured per the JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 24.2.4 Heat Sinks and Junction-to-Case Thermal Resistance For the power values the device is expected to operate at, it is anticipated that a heat sink will be required. A preliminary estimate of heat sink performance can be obtained from the following first first-cut MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 113 Thermal approach. The thermal resistance is expressed as the sum of a junction to case thermal resistance and a case-to-ambient thermal resistance: RJA = RJC + RCA where: RJA = junction to ambient thermal resistance (C/W) RJC = junction to case thermal resistance (C/W) RCA = case to ambient thermal resistance (C/W) RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This first-cut approach overestimates the heat sink size required, since heat flow through the board is not accounted for, which can be as much as one-third to one-half of the power generated in the package. Accurate thermal design requires thermal modeling of the application environment using computational fluid dynamics software which can model both the conduction cooling through the package and board and the convection cooling due to the air moving through the application. Simplified thermal models of the packages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. More detailed thermal models can be made available on request. The thermal performance of devices with heat sinks has been simulated with a few commercially available heat sinks. The heat sink choice is determined by the application environment (temperature, air flow, adjacent component power dissipation) and the physical space available. Because of the wide variety of application environments, a single standard heat sink applicable to all cannot be specified. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 114 Freescale Semiconductor Thermal Table 81 shows the heat sink thermal resistance for TePBGA II package with heat sinks, simulated in a standard JEDEC environment, per JESD 51-6. Table 81. Thermal Resistance with Heat Sink in Open Flow (TePBGA II) Thermal Resistance Heat Sink Assuming Thermal Grease Air Flow (/W) AAVID 30 x 30 x 9.4 mm Pin Fin Natural Convection 0.5 m/s 1 m/s 2 m/s 4 m/s 13.1 10.6 9.3 8.2 7.5 11.1 8.5 7.7 7.2 6.8 11.3 9.0 7.8 7.0 6.5 9.7 7.7 6.8 6.4 6.1 AAVID 31 x 35 x 23 mm Pin Fin Natural Convection 0.5 m/s 1 m/s 2 m/s 4 m/s AAVID 43x 41x 16.5mm Pin Fin Natural Convection 0.5 m/s 1 m/s 2 m/s 4 m/s Wakefield, 53 x 53 x 25 mm Pin Fin Natural Convection 0.5 m/s 1 m/s 2 m/s 4 m/s Heat sink vendors include the following: Aavid Thermalloy www.aavidthermalloy.com Alpha Novatech www.alphanovatech.com International Electronic Research Corporation (IERC) www.ctscorp.com Millennium Electronics (MEI) www.mei-thermal.com MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 115 Thermal Tyco Electronics Chip CoolersTM www.chipcoolers.com Wakefield Engineering www.wakefield.com Interface material vendors include the following: Chomerics, Inc. www.chomerics.com Dow-Corning Corporation Dow-Corning Electronic Materials www.dowcorning.com Shin-Etsu MicroSi, Inc. www.microsi.com The Bergquist Company www.bergquistcompany.com 24.3 Heat Sink Attachment The device requires the use of heat sinks. When heat sinks are attached, an interface material is required, preferably thermal grease and a spring clip. The spring clip should connect to the printed circuit board, either to the board itself, to hooks soldered to the board, or to a plastic stiffener. Avoid attachment forces that can lift the edge of the package or peel the package from the board. Such peeling forces reduce the solder joint lifetime of the package. The recommended maximum compressive force on the top of the package is 10 lb force (4.5 kg force). Any adhesive attachment should attach to painted or plastic surfaces, and its performance should be verified under the application requirements. 24.3.1 Experimental Determination of the Junction Temperature with a Heat Sink When a heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimize the size of the clearance to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction to case thermal resistance. TJ = TC + (RJC x PD) where: TJ = junction temperature (C) TC = case temperature of the package (C) MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 116 Freescale Semiconductor System Design Information RJC = junction to case thermal resistance (C/W) PD = power dissipation (W) 25 System Design Information This section provides electrical and thermal design recommendations for successful application of the MPC8377E. 25.1 PLL Power Supply Filtering Each of the PLLs listed above is provided with power through independent power supply pins. The AVDD level should always be equivalent to VDD, and preferably these voltages will be derived directly from VDD through a low frequency filter scheme. There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide five independent filter circuits as illustrated in Figure 65, one to each of the five AVDD pins. By providing independent filters to each PLL, the opportunity to cause noise injection from one PLL to the other is reduced. This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL). Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value capacitor. Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of package, without the inductance of vias. Figure 65 shows the PLL power supply filter circuit. 10 VDD 2.2 F 2.2 F Low ESL Surface Mount Capacitors AVDD (or L2AVDD) GND Figure 65. PLL Power Supply Filter Circuit 25.2 Decoupling Recommendations Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the device system, and the device itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each VDD, OVDD, GVDD, and LVDD pins of the device. These decoupling capacitors should receive their power from separate VDD, OVDD, GVDD, LVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly under the device using a standard escape pattern. Others may surround the part. MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 117 System Design Information These capacitors should have a value of 0.01 or 0.1 F. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors--100-330 F (AVX TPS tantalum or Sanyo OSCON). 25.3 Connection Recommendations To ensure reliable operation, it is highly recommended that unused inputs be connected to an appropriate signal level. Unused active low inputs should be tied to OVDD, GVDD, or LVDD as required. Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, GVDD, LVDD, OVDD, and GND pins of the device. 25.4 Output Buffer DC Impedance The device drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver type (open drain for I2C). To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 66). The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then, Z0 = (RP + RN)/2. OVDD RN SW2 Data Pad SW1 RP OGND Figure 66. Driver Impedance Measurement MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 118 Freescale Semiconductor Ordering Information The value of this resistance and the strength of the driver's current source can be found by making two measurements. First, the output voltage is measured while driving logic 1 without an external differential termination resistor. The measured voltage is V1 = Rsource x Isource. Second, the output voltage is measured while driving logic 1 with an external precision differential termination resistor of value Rterm. The measured voltage is V2 = (1/(1/R1 + 1/R2)) x Isource. Solving for the output impedance gives Rsource = Rterm x (V1/V2 - 1). The drive current is then Isource = V1/Rsource. Table 82 summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD, nominal OVDD, 105C. Table 82. Impedance Characteristics Local Bus, Ethernet, DUART, Control, Configuration, Power Management 42 Target 42 Target NA PCI Signals (not including PCI output clocks) 25 Target 25 Target NA PCI Output Clocks (including PCI_SYNC_OUT) 42 Target 42 Target NA Impedance DDR DRAM Symbol Unit RN RP Differential 20 Target 20 Target NA Z0 Z0 ZDIFF W W W Note: Nominal supply voltages. See Table 2, Tj = 105C. 25.5 Configuration Pin Muxing The device provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 k on certain output pins (see customer visible configuration pins). These pins are generally used as output only pins in normal operation. While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins while HRESET is asserted, is latched when PORESET deasserts, at which time the input receiver is disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured. 25.6 Pull-Up Resistor Requirements The device requires high resistance pull-up resistors (10 k is recommended) on open drain type pins including I2C pins, Ethernet Management MDIO pin and IPIC interrupt pins. For more information on required pull-up resistors and the connections required for the JTAG interface, see AN3665, "MPC837xE Design Checklist." 26 Ordering Information Ordering information for the parts fully covered by this specification document is provided in Section 26.1, "Part Numbers Fully Addressed by This Document." MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 119 Ordering Information 26.1 Part Numbers Fully Addressed by This Document Table 83 provides the Freescale part numbering nomenclature for the MPC8377E. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office. In addition to the processor frequency, the part numbering scheme also includes an application modifier which may specify special application conditions. Each part number also contains a revision code which refers to the die mask revision number. Table 83. Part Numbering Nomenclature MPC 8377 E Encryption Acceleration C Temperature Range 1 ZQ Package 2 AF e300 core Frequency 3, 4 D DDR Data Rate A Revision Level Product Part Code Identifier MPC 8377 Blank = Not included Blank = 0C (Ta) to VR = Pb-free 125C (Tj) E = included 689 TePBGA II C = -40C (Ta) to 125C (Tj) AL = 667 MHz G = 400 MHz Contact local Freescale AJ = 533 MHz F = 333 MHz AG = 400 MHz D = 266 MHz sales office AN = 800 MHz Note: Contact local Freescale office on availability of parts with an extended temperature range. 2 See Section 22, "Package and Pin Listings," for more information on the available package type. 3 Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other maximum core frequencies. 4 An 800 MHz device is not supported in extended temperature (-40 C to 125 C). 1 Table 84 lists the available core and DDR data rate frequency combinations. Table 84. Available Parts (Core/DDR Data Rate) MPC8377E 800 MHz/400 MHz 667 MHz/400 MHz 533 MHz/333 MHz 400 MHz/266 MHz MPC8378E 800 MHz/400 MHz 667 MHz/400 MHz 533 MHz/333 MHz 400 MHz/266 MHz MPC8379E 800 MHz/400 MHz 667 MHz/400 MHz 533 MHz/333 MHz 400 MHz/266 MHz MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 120 Freescale Semiconductor Ordering Information Table 85 shows the SVR and PVR settings by device. Table 85. SVR and PVR Settings by Product Revision SVR Device Package Rev 1.0 MPC8377 MPC8377E MPC8378 TePBGA II MPC8378E MPC8379 MPC8379E 0x80C4_0010 0x80C3_0010 0x80C2_0010 0x80C4_0021 0x80C3_0021 0x80C2_0021 0x80C7_0010 0x80C6_0010 0x80C5_0010 Rev. 2.1 0x80C7_0021 0x80C6_0021 0x80C5_0021 0x8086_1010 0x8086_1011 Rev. 1.0 Rev. 2.1 PVR 26.2 Part Marking Parts are marked as in the example shown in Figure 67. MPCnnnnetppaaar core/platform MHZ ATWLYYWW CCCCC *MMMMM YWWLAZ TePBGA II Notes: ATWLYYWW is the traceability code. CCCCC is the country code. MMMMM is the mask number. YWWLAZ is the assembly traceability code. Figure 67. Freescale Part Marking for TePBGA II Devices MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 121 Document Revision History 27 Document Revision History Table 86 provides a revision history for this hardware specification. Table 86. Document Revision History Revision 2 Date 10/2009 * * * * * * * * * * * * * * * 1 Substantive Change(s) In Table 3, "Recommended Operating Conditions," added "Operating temperature range" values. In Table 5, "MPC8377E Power Dissipation 1," corrected maximal application for 800/400 MHz to 4.3 W. In Table 5, "MPC8377E Power Dissipation 1," added a column for "Typical Application at Tj = 65C (W)". In Table 5, "MPC8377E Power Dissipation 1," added a column for "Sleep Power at T j = 65C (W)". In Table 10, removed overbar from CFG_CLKIN_DIV. In Table 16, "Current Draw Characteristics for MVREF," updated IMVREF maximum value for both DDR1 and DDR2 to 600 and 400 A, respectively. Also, updated Note 1 and added Note 2. In Table 19, "DDR1 and DDR2 SDRAM Input AC Timing Specifications," column headings renamed to "Min" and "Max". Footnote 2 updated to state "T is the MCK clock period". In Table 19, "DDR1 and DDR2 SDRAM Input AC Timing Specifications," and Table 20, "DDR1 and DDR2 SDRAM Output AC Timing Specifications," clarified that the frequency parameters are data rates. In Table 28, "RMII Transmit AC Timing Specifications," updated tRMTDXI to 2.0 ns. In Table 59, Gen 1i/1.5G Receiver AC Specifications," and Table 61, Gen 2i/3G Receiver AC Specifications," corrected titles from "Transmitter" to "Receiver". In Table 71, "TePBGA II Pinout Listing," removed pin THERM0; it is now Reserved. Also added 1.05 V to VDD pin. In Table 73, "Operating Frequencies for TePBGA II," corrected "DDR2 memory bus frequency (MCK)" range to 125-200. In Table 78, "e300 Core PLL Configuration," added 3.5:1 and 4:1 core_clk: csb_clk ratio options. In Table 79, "Example Clock Frequency Combinations," updated column heading to "DDR data rate" . In Section 20.2, "SPI AC Timing Specifications," corrected tNIKHOX and tNEKHOX to tNIKHOV and tNEKHOV, respectively. 02/2009 * In Table 3, "Recommended Operating Conditions," added two new rows for 800 MHz, and created two rows for SerDes. In addition, changed 666 to 667 MHz. * In Table 5, "MPC8377E Power Dissipation 1," added Notes 4 and 5. In addition, changed 666 to 667 MHz. * In Table 12, "DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V," Table 20, "DDR1 and DDR2 SDRAM Output AC Timing Specifications," and Table 71, "TePBGA II Pinout Listing," added footnote to references to MVREF, MDQ, and MDQS, referencing AN3665, MPC837xE Design Checklist. * In Table 20, updated tDDKHCX minimum value for 333 MHz to 2.40. * In Table 71, "TePBGA II Pinout Listing," added footnote to USBDR_STP_SUSPEND and modified footnote 10 and added footnote 13. * In Table 73, "Operating Frequencies for TePBGA II," changed 667 to 800 MHz for core_clk. * In Table 79, "Example Clock Frequency Combinations," added 800 MHz cells for e300 core. * Updated part numbering information in AF column in Table 83, "Part Numbering Nomenclature." In addition, modified extended temperature information in notes 1 and 4. * In Table 84, "Available Parts (Core/DDR Data Rate)," added new row for 800/400 MHz. 12/2008 Initial public release. 0 MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 122 Freescale Semiconductor Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC8377E PowerQUICCTM II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 123 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3au, 802.3ab, 1588 are registered trademarks of the Institute of Electrical and Electronics Engineers, Inc. (IEEE). This product is not endorsed or approved by the IEEE. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc., 2009. All rights reserved. Document Number: MPC8377EEC Rev. 2 10/2009 |
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